OpenCores MAC timing contraints

[Altera_Forum]

Hi, 

 I try to make a design using the OpenCores Eth 10/100 but have a lot of Timing Requirements not met. Could someone who succeed in similar work share its timing constraints file (.sdc)? I have several clocks like 'rx_busy_dc_reg' that are not constrainted...  TIA, Fred

[Altera_Forum]

--- Quote Start ---  Hi, I have several clocks like 'rx_busy_dc_reg' that are not constrainted...   --- Quote End ---   Those are not clocks; rx_busy_dc_reg and similar are actually registers.  Your problem is that such registers in OpenCores mac have different input and output clocks: you have the main system clock on one side and the mac tx or rx clock on the other. Since they generally have different frequencies (i.e. 100MHz for main clock and 25MHz for rx/tx clock), you need to apply set_multicycle_path directives to these paths in the .sdc file.

[Altera_Forum]

Thanks, Cris, I will try this. 

But (sorry to insist :-), if you had an .SDC example for me... Thanks !

[Altera_Forum]

I'm afraid. I don't have a sample. 

I searched one of my designs where I used OC mac, but I found that I rather used a crude method to bypass the warning: I put set_false_path between mac rx/tx clocks and the system clocks. AFAIK I've never had timing problems. I'm confident this is not an issue, since rx/tx clock 25MHz frequency is quite low and the timing requirements are easily met.