PLL output to general i/o pin

Altera_Forum · ‎02-20-2012

Quartus V7.2 SP2

Device EP3C25E144C8

I have a 48Mhz oscillator connected to the dedicated clock input pins CLK2 and CLk5. I also have a 23.5Mhz clock signal coming in on a standard i/o pin (pin 103).

Using one or other of these clocks I need to generate a 33MHz clock to output on two other standard i/o pin (pins 50 & 136).

My understanding is that it isn't possible to drive the ALTPLL megafunction with a standard i/o pin so I am driving the PLL with the 48MHz clock and then scaling it to get a 66MHz clock out which I then divide in the hdl to get two 33MHz clocks that I connect to the output pins.

module lcd_ctlr
(
    clk,                       // 48MHz
    pix_clk_in,            // 23.5Mhz
    dot_clk_out_lcd0,  // 33Mhz		
    dot_clk_out_lcd1,  // 33Mhz		
);
input clk;
input pix_clk_in;
output dot_clk_out_lcd0;
output dot_clk_out_lcd1;
reg dot_clk_out_lcd0 = 1'b1;
reg dot_clk_out_lcd1 = 1'b1;
wire dclk_src;
pll dclk_pll
(
	.inclk0		(clk),
	.c0			(dclk_src)
);
always @(posedge dclk_src) 
begin
    dot_clk_out_lcd0 <= ~dot_clk_out_lcd0;
    dot_clk_out_lcd1 <= ~dot_clk_out_lcd1;	
end
endmodule

The problem I have is that the 33MHz clock output on the pin doesn't seem to be 33Mhz when I look at it with a scope. Oddly it seems to change frequency when I don't significantly change the hdl and just do a recompile.

I have seen that there can be timing problems when not using a dedicated PLL output pin as a clock output but I'm hoping to try and generate a 33MHz output without having to redesign the hardware.

Can anyone see something that I'm doing wrong or suggest an alternative way of solving this problem? Thanks.

Altera_Forum · ‎02-20-2012

--- Quote Start ---

I have seen that there can be timing problems when not using a dedicated PLL output pin as a clock output but I'm hoping to try and generate a 33MHz output without having to redesign the hardware.

--- Quote End ---

"Timing problems" means slightly increased timing uncertainty and jitter. But it will always correctly transmit the PLL clock.

You don't show the PLL parameters, but provided they are correct, which isn't a big thing for a 48 to 66 MHz converting PLL, the design should work.

Can you tell about the design enviroment? Is it a development kit or a custom designed board? In the latter case, there may be a problem of not providing a clean PLL input clock or other design problems that cause PLL unlock. Monitoring the PLL lock output can help to identify problems of this kind.

Altera_Forum · ‎02-21-2012

Thanks FvM. Your suspicion was correct the 48MHz wasn't being generated correctly. Correcting the hardware has fixed the problem.