Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21602 Discussions

Problem In Reading SSRAM On Cycone III

Altera_Forum
Honored Contributor II
1,246 Views

Hi, 

 

I am using Cyclne III Kit ... Which has External SSRAM on it. I am trying to perform read and write from it. I have coded small state machine which generates control signals to SSRAM. 

 

The writes are working good in both RTL and Gate Level Simulation. But I observed Read is not happening in Gate Level Simulation.  

 

I have seen data floating on DQ at Rising edge of the clock. But my registred read data is 32'hXXXXXXXXX.  

 

Please anybody help to figure out the mistake ? 

 

Thanks, 

Ganapathi.
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
540 Views

What are you using for a simulation model for the SSRAM? Which SSRAM device is on the board? 

 

Jake
0 Kudos
Altera_Forum
Honored Contributor II
540 Views

I am using IS61LVPS25636A SRAM simulation model. The SRAM on the board is IS61LPS25636A.  

 

Hope your reply, 

Ganapathi
0 Kudos
Altera_Forum
Honored Contributor II
540 Views

Hi, were you able to use the SSRAM successfully? 

i can't get the SSRAM to work properly, i can't write to the SSRAM properly. can i have some example code? 

 

-AK
0 Kudos
Reply