Problem in NiosII based design with different instructions and data memories

[Altera_Forum]

Hello, 

 I am a beginner in using qsys for systems design. I have made a simple design that contains: - niosII processor ("e" version) - on chip memory for instructions connected to the niosII instruction_master port - on chip memory for data connected to the niosII data_master port - jtag UART connected to the niosII data_master port  Then, I have made a simple project "Hello world" using the the "Nios II software build tool".  The problem is when I ran this project, I do not get the message "Hello from NiosII" on the "niosII Console". However, when I use the same on chip memory for data and instructions (connected to data master port and instruction master port at the same time), I get the message.  So, would you please, explain to me why my design does not work with two on chip memories (one for data and one for instructions) and how can I fix this?  I am working with Quartus prime 17.0 on Attila Arria 10 board.  Thanks.

[Altera_Forum]

I think that in order to load the software correctly, the memory for instructions needs to be also connected to the data master port. 

You must also check when generating the bsp that all your linker sections point to the correct memory (i.e. .text to the instruction memory, .bss, .ro and .rw (IIRC) to the data memory).

[Altera_Forum]

--- Quote Start ---  I think that in order to load the software correctly, the memory for instructions needs to be also connected to the data master port. You must also check when generating the bsp that all your linker sections point to the correct memory (i.e. .text to the instruction memory, .bss, .ro and .rw (IIRC) to the data memory).  --- Quote End ---    Thank you. It works. However, this means to modify, manually, the linker every time I make modification in my design.