Programmer file not update after I recompile the VHDL file

[Altera_Forum]

I am working on Cyclone II FPGA EP2C8F256, and using USB-Blaster in JTAG mode to program the .pof or .sof file. Every time after I made some changes to my VHDL code, recompile the project and program the FPGA, my FPGA always ran the previous code, unless I close the project and reopen it to recompile and re-program. I don't know why I had to reopen the project for the programmer file to update. I am using Quartus II 8.0. Thanks.

[Altera_Forum]

The Quartus compile command outputs a sof file. If you need a pof file you will need to use the convert programming file command every time you compile and want to run on hardware.

[Altera_Forum]

--- Quote Start ---  The Quartus compile command outputs a sof file. If you need a pof file you will need to use the convert programming file command every time you compile and want to run on hardware.  --- Quote End ---    The file I chose in programmer page is .sof file. The .sof file running on hardware is not updating after I re-compile.

[Altera_Forum]

Hi, 

 You can check the output_files directory and look in the <project_name>.asm.rpt file and check if the programming files were generated for the most recent compilation. This file will report if there are any errors or any programming files are not generated. Also, another option is that sometimes quartus behaves odd if the system is out of memory, so you many want to try closing other applications and try again. Hope this helps!  Thanks,

[Altera_Forum]

Can you try to reselect the sof file again in programmer?