I'm having an issue with timing analyzer in Quartus Prime 18.1_SP1. (I'm forced to use this version for product software acceptance reasons).
A few reset nets are detected as clock nets, and show up in the Unconstrained Clocks report. How can I resolve this in the SDC constraints? Simply adding min/max delays doesn't resolve it (but I thought they would be appropriate for a reset net). I don't think it's helpful to define them as clocks since that would overconstrain the design.
I think you should look closer at why they are being interpreted as clocks. Can you post some code? If you have put resets in the sensitivity list with the intention to create asynchronous resets (my guess), you have to code them appropriately so they don't get interpreted incorrectly.
You may check out the documentation below.
Intel® Quartus® Prime Pro Edition User Guide: Scripting
Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer
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