Hello,
So for my product, I have already coded an SPI shift registers, then, in another module, I am comparing magnitude of 2 seperate bytes with upper and lower limit then simply output to some pin in a non-deterministic fashion, there is not some other dataset to be synched with. Not much fancy. Clocks to be sampled are running @ 150Mhz or 108Mhz.
In all I have 4 clock pins, connected as such, with an active oscillator.
Possibly I would like to re-use the calculation logic and simply change clocks.
Here is some rough sketch idea, sorry for my little experience but I started verilog for this project 2 weeks ago, I had studied it a bit before.
Basically I am asking help on how to get started as it regards the primitive syntax, I would prefer a rough sketch, yet detailed enough that I can be on my way. An example with some directive on how to accomplish a bug free switchover using my particular setup.
Thank you.
always @(posedge main_clk)begin
if(silence_inv==1'b0) begin
calculation
....
end
end
always @(posedge mcu_clk)begin
if(silence_inv==1'b1) begin
calculation
....
end
end
