Read from memory

[Yassine-Ca]

Hello,

           I'm working on DE1-SoC Cyclone V FPGA.

            I have prgrammed the FPGA to store a static data to the onchip memory created on Platform Designer, this generated the definition files in verilog, containing JTAG and OnChip memory.

           After definition in Quartus and add all the files in the project, then I compile and the sof file has been sent to the FPGA.

            Now I using a tcl commands to read from the memory, my problem is how to access the memory without address, any other way as sending data continously or each lap of time to JTAG?

             I tried Platform Designer to get an adress but It doesn't assign unless you configure a master.

              Your help please.

               Regards.

[FvM]

Hi,
it's unclear which interface logic you are using to read from memory. There can be a JTAG controlled debug master (JTAG to Avalon Host Bridge) as well as custom logic connecting second memory port through conduit. Would be helpful to see a block diagram of your design. 

Regards
Frank

[Yassine-Ca]

Hi,

            I maked a mistake using non JTAG Master, now I use it, please find image attached.

These the code generated by Platform Designer:
module mem (
input wire clk_in_clk, // clk_in.clk
input wire memory_clk2_clk, // memory_clk2.clk
input wire memory_reset2_reset, // memory_reset2.reset
input wire memory_reset2_reset_req, // .reset_req
input wire [11:0] memory_s2_address, // memory_s2.address
input wire memory_s2_chipselect, // .chipselect
input wire memory_s2_clken, // .clken
input wire memory_s2_write, // .write
output wire [7:0] memory_s2_readdata, // .readdata
input wire [7:0] memory_s2_writedata, // .writedata
input wire reset_in_reset_n // reset_in.reset_n
);

           I could connect into the DE1 board over the tcl, but I had the problem to continue, can you assist me in the tcl code attached.

           Regards.

[sstrell]

The address is right there in PD from 0x0 to 0xfff.

[Yassine-Ca]

Hi,

                 Yes, Because I modified the design from JTAG to JTAG Bridge.

                   I'm trying to see if any communication can be done, and let you know.

                    Regards.

[Yassine-Ca]

Hi,

                 When I execute tcl scripts, I get these errors:

Error: Failed to read data from FPGA memory. Result: ERROR: JTAG communication error is detected. It can be caused by the hardware failure and signal integrity in the JTAG chain. Try to restart.

while executing
"error "Error: Failed to read data from FPGA memory. Result: $result""
invoked from within
"if {$data_from_fpga == ""} {
error "Error: Failed to read data from FPGA memory. Result: $result"
} else {
puts "Debug: Data read from FPGA at..."
(file "receive_altera_FPGA.tcl" line 72)
------------------------------------------------

Error: Error executing TCL script:
------------------------------------------------
Error: Failed to read data from FPGA memory. Result: ERROR: JTAG communication error is detected. It can be caused by the hardware failure and signal integrity in the JTAG chain. Try to restart.

while executing
"error "Error: Failed to read data from FPGA memory. Result: $result""
invoked from within
"if {$data_from_fpga == ""} {
error "Error: Failed to read data from FPGA memory. Result: $result"
} else {
puts "Debug: Data read from FPGA at..."
(file "receive_altera_FPGA.tcl" line 72)
------------------------------------------------

                        Note that when I execute the script, I see that RX and TX LEDs inside FPGA near JTAG are flashing.

                         Please find attached the tcl file in text format.

                         Regards

[Yassine-Ca]

Hi,

        I have created tcl file, but I need to execute both of the commands quartus_stp and quartus_sh in the same file.

        I use read_content_from_memory which is quartus_stp instruction, but I need to execute commands inside the same file relative to quartus_sh, if any solution with two files that 1 execute from other?

         Regards.

[RichardTanSY_Altera]

Unfortunately, we do not provide support for writing custom scripts.

That being said, you can refer to this user guide, which provides details on how to use command-line executables in scripts to control Quartus software alongside other tools:

https://www.intel.com/content/www/us/en/docs/programmable/683325/18-1/using-command-line-executables-in-scripts.html

Regards,

Richard Tan

[Yassine-Ca]

Hi,

            I tried the script to see if any editable memory, but I get : Warning (16702): No editable memory instance was found.
Editable memory instances: ERROR: No editable memory instances found.

           I use OnChip Memory writable, please image attached.

The TCL Script:

set hw_name "DE-SoC \[USB-1\]"
set dev_name "@2: 5CSE(BA5|MA5)/5CSTFD5D5/.. (0x02D120DD)"

# List editable memory instances
puts "Listing editable memory instances..."
set mem_instances [get_editable_mem_instances -hardware_name $hw_name -device_name $dev_name]
puts "Editable memory instances: $mem_instances"

if {[llength $mem_instances] == 0} {
puts "ERROR: No editable memory instances found."
exit 1
}

         Regards.

[RichardTanSY_Altera]

You may checkout the In System Memory Content Editor (ISMCE) tool, to view and update memories and constants at runtime through the JTAG interface.

https://www.intel.com/content/www/us/en/docs/programmable/683819/24-3/in-system-modification-of-memory-and-26355.html

You are using JTAG to Avalon® Master Bridge, which is the Debug Agent Providing Service for system console.

In that case, you can use System Console debug tool for debugging.

Regards,

Richard Tan

[Yassine-Ca]

Hi,

                Thank you for your reply.

                  I used system console, I write the commands as open_service ....then It works successfully, but when I write the commands as: master_read_memory, master_read_16, master_read_8 and even master_read_32, I get :

WARNING: This transaction has not completed in 10 seconds. System Console will keep trying for 50 more seconds.

GRAVE: master_read_memory: This transaction did not complete in 60 seconds. System Console is giving up.

                   Can you tell me if may be something is missing on the quartus project or OnChip memory configuration in Platform Designer.

                    Regards

[RichardTanSY_Altera]

The best way is to go through the application note and run successfully using the design example.

Alternatively, you can go through the steps using your design and verify the signal integrity/clock toggling of the JTAG chain in step 3.

Application Note:

https://www.intel.com/content/www/us/en/docs/programmable/826921/24-3/about-this-application-note.html

Arria 10 example design:

https://www.intel.com/content/www/us/en/design-example/842175/arria-10-system-console-getting-started-design.html

Regards,

Richard Tan

[RichardTanSY_Altera]

Hi,

Do you need any further assistance from my side?

Regards,

Richard Tan

[Yassine-Ca]

Hello,

             I tried many time using System console with the following commands:
%get_service_paths master
/devices/5CSE(BA5|MA5)|5CSTFD5D5|..@2#USB-1#DE-SoC/(link)/JTAG/alt_sld_fab_sldfabric.node_0/phy_0/jtag_master.master

% open_service master "/devices/5CSE(BA5|MA5)|5CSTFD5D5|..@2#USB-1#DE-SoC/(link)/JTAG/alt_sld_fab_sldfabric.node_0/phy_0/jtag_master.master"

% is_service_open master "/devices/5CSE(BA5|MA5)|5CSTFD5D5|..@2#USB-1#DE-SoC/(link)/JTAG/alt_sld_fab_sldfabric.node_0/phy_0/jtag_master.master"
1

% master_read_memory "/devices/5CSE(BA5|MA5)|5CSTFD5D5|..@2#USB-1#DE-SoC/(link)/JTAG/alt_sld_fab_sldfabric.node_0/phy_0/jtag_master.master" 0x00000000 8  

            When I writed the last comman system console displays the same issue even I try to follow the link instructions.

           Regards.

[Yassine-Ca]

Hi,

      Thank you, I used Eclipse with NIOS II and it is working.

       I need now to send the program into flash memory, In platform Designer I choose Generic QUAD SPI Controller II, but I don't know which configuration device type do I need to choose, I have DE1-SoC Cyclone V FPGA. The memory i'll use is 32 GB.

     Regards.

[RichardTanSY_Altera]

I'm pleased to know that the initial issue has been resolved.

For your follow-up question, kindly file a new case in forum so we can address it in detail.

Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.

Thank you and have a great day!

Best Regards,

Richard Tan