Reference clocks for Transceiver PLLs

[Altera_Forum]

Hi, 

 I'm having issues with transceivers, which I have not used before. Currently I am trying to get a 1.25GHz clock from a Transceiver PLL. The clock I am trying to use as a reference clock is the same one I have used in other areas of my project. When Compilation results in an error saying "Error(175020): The Fitter cannot place logic pin in region (78, 147) to (78, 153), to which it is constrained, because there are no valid locations in the region for logic of this type". I'm guessing this means I am using a clock from the wrong region as a reference to the Transceiver PLL. So my question is: How do we know which clocks can be used as reference for Transceiver PLLs? Sorry if this question is a bit basic.  Thanks for your time, ap29

[Altera_Forum]

Hi, 

 Can you tell about the device and kit used? Check-in handbook or refer some reference design if available.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)

[Altera_Forum]

--- Quote Start ---  Hi,  Can you tell about the device and kit used? Check-in handbook or refer some reference design if available.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)  --- Quote End ---    I'm using a board with an Arria 10. From the Arria 10 Transceiver Guide, there are supposed to be refclks that run down either side of the board and can feed any transceiver PLLs. From the user guide of my board though, de5a_net_e1, there are QSFP+ ref clocks and an I2C programmable oscillator that can apparently be used as a ref clock. For now, I guess I will try to the QSFP+ ref clock and see if the compilation completes.

[Altera_Forum]

Hi, 

 Okay, If you are facing the same issue compare with reference design OR the pin connection guidelines in below links. http://www.alterawiki.com/wiki/arria_10_transceiver_phy_design_examples https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/dp/arria-10/pcg-01017.pdf  Let me know if this has helped resolve the issue you are facing or if you need any further assistance.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)

[Altera_Forum]

--- Quote Start ---  Hi,  Okay, If you are facing the same issue compare with reference design OR the pin connection guidelines in below links. http://www.alterawiki.com/wiki/arria_10_transceiver_phy_design_examples https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/dp/arria-10/pcg-01017.pdf  Let me know if this has helped resolve the issue you are facing or if you need any further assistance.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)  --- Quote End ---    I fixed my issue by specifically using a QSFP reference clock. I guess it is intended for driving the transceiver PLL as it is located in the correct place. Your links, however, seem very helpful for other parts of my project. Thanks for linking them. I consider the problem solved now, Thanks.