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Reset Vector - NIOS

MK_ABQ
New Contributor II
3,083 Views

Hello,

I have a reference NIOS project in which the reset vector memory is selected as an external flash. I opened platform designer and found the following information. Picture attached below.

MK_ABQ_0-1675116973530.png

Can you help to answer my following questions?. I did go through the embedded handbook, and NIOS user guide but could not get a specific answer. Can  you help?

 

Q1)  Why is the "reset vector" field greyed out here?. 

Q2) Which address will be taken into account for the reset vector?. 0x08b0_0000 (or) 0x18b0_0000?

 

 

Thanks

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KellyJialin_Goh
Employee
3,059 Views

Hi MK,

Greetings and welcome to Intel's forum.

There is not specific reason why it is greyed out. It is according to the base address you set in Platform Designer. You have the flash address set to 0x10000000, and the offset to 0x08b00000. Therefore, flash will start access at 0x18b00000.


Hope this clarifies your doubts.

Thank you.


Regards,

Kelly



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22 Replies
sstrell
Honored Contributor III
2,916 Views

It's based off the base address you set in Platform Designer.  So it looks like in PD you have this flash set at address 0x10000000.  You set the offset to 0x08b00000, so the Nios accesses the flash starting at 0x18b00000.

KellyJialin_Goh
Employee
3,060 Views

Hi MK,

Greetings and welcome to Intel's forum.

There is not specific reason why it is greyed out. It is according to the base address you set in Platform Designer. You have the flash address set to 0x10000000, and the offset to 0x08b00000. Therefore, flash will start access at 0x18b00000.


Hope this clarifies your doubts.

Thank you.


Regards,

Kelly



MK_ABQ
New Contributor II
2,880 Views

Thanks for the clear explanation. 

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MK_ABQ
New Contributor II
2,858 Views

I would like to reopen this thread with further question on reset vector for Nios.

 

Q1) You have mentioned Nios access the flash starting at " 0x18b0_0000".  Does this 0x18b0_0000 represent an address present in Flash?. 

Here is the picture of the platform designer for my system.

MK_ABQ_0-1675291160594.png

Here is a picture from the board test gui that has come along with the development kit. The gui mentions that the flash address  is only between 0x0000_0000 to 0x0FFF_FF80. 

MK_ABQ_1-1675291228712.png

And the QSF of this project shows only 26 address lines for the flash. so what is the actual memory of the flash we are talking about here?

note that the project can compile fine, and the nios can boot up, and TCP is up and running.

 

Q2) what does the reset vector address actually signify?. Does pointing the reset address vector to 0x18b0_0000 and choosing the reset vector memory as "ext_flash.uas" change/write something to the flash?. what does this address location denote?. 

Note that we just pointed out this reset vector location to the non volatile memory, but then we only generate SOF, and program into the FPGA. never generated any pof or flash specific file. So, it  makes me wonder what this reset vector actually signifies, and how come it works even if we point the reset vector memory to flash, despite not programming anything to flash!.

 

p.s: please feel free to write back with more questions incase if my statements or questions are not clear. I am happy to explain. 

Thanks

 

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sstrell
Honored Contributor III
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1) As already stated, the flash in your system starts at 0x10000000 and verified in the address map you've shown.  The offset you've selected for the reset vector must be within the range of the flash, and it is.  The board test system is a completely different design so its setup doesn't apply to your design.  Addressing is specific to the host you connect to, in this case, the Nios processor.

2) This is the address where the Nios will start running code from.  It doesn't do anything to the flash.  The flash (or whatever memory is attached) must be set up appropriately to start running code at that address.  On the dev kit, the flash is already configured though you can change it if you want to using the flash programmer tool in Quartus.

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KellyJialin_Goh
Employee
2,833 Views

Hi MK,

1) The flash in your system starts at 0x10000000 and verified in the address map with your attached screenshot. The offset you selected for the reset vector must be within the range of the flash, and it is. 

The board test system is a different design so it is not compatible to your design. Addressing is specific to NIOS processor, which is also your host..


2) This is the address where the NIOS will start running code from and the flash will not be affected. The flash (and the memory that are attached in screenshot of GUI) must be set correctly to start running code from that address.

The flash is already configured on the Development Kit but you can still change it by using the flash programmer tool in Quartus.


Hope this clarifies your doubts.


Thank you.

Regards,

Kelly


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MK_ABQ
New Contributor II
2,819 Views

Hello,

"This is the address where the Nios will start running code from.  It doesn't do anything to the flash."

"This is the address where the NIOS will start running code from and the flash will not be affected."

 

 -- When you say the Nios will start running the code from that specific address location, then doesn't it mean that there should be something written to that address location in flash?. What is the meaning of running the code from that address?. I would think a piece of code is copied to starting from that specific address location and then start running the code. Can you throw a bit more light on this?

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sstrell
Honored Contributor III
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Yes.  That's the point of a reset vector, to specify where to start running code from.  So if the flash is set to be at that address, there has to be code there on the flash at that address.  Not sure I understand your confusion.

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MK_ABQ
New Contributor II
2,806 Views

So my confusion is the following :

 

1) If I set the nios reset vector to a flash address, then as per my understanding, there has to be a code there on the flash at that address. The piece of code which is mentioned here is the .pof or some equivalent file of the design in flash, with nios in it. The system that I am building in Qsys will be eventually converted into a bit stream, and then loaded into the flash. This is the same piece of code that the reset vector points to. Am I correct?

 

2)  The reset vector address is set as  0x18b00000 and the flash base address is set as  0x10000000, and you have mentioned "So if the flash is set to be at that address, there has to be code there on the flash at that address".  So as per flash address, we need 28 address lines to map to 0x1000_0000 ( converted this to binary and the 28th bit high. But, as per the development kit schematic, there are only 27 address lines as per schematic. p.s: see below. So how is the address 0x1000_0000 accessed? There is no such address in flash memory. 

MK_ABQ_0-1675450618646.png

 

 

The above two questions are for one specific design that I worked with. 

 

The following questions are for a completely different design. But the question is related to reset vector, and using external flash as reset vector memory. 

 

Q1) Does the reset vector specify any value for reset to nios core?, apart from mentioning the starting location of the code?

Q2) In this specific new project, I specified the reset vector to point to external flash. I just generated a sof and programmed only my FPGA, and the design was still working. I never touched the flash. So how did this design work?. I pointed the reset vector to external flash, and i never programmed the flash, but just loaded the fpga with sof, opened eclipse, ran my software project in NIOS, and NIOS was able to boot up and perform the required TCP server action. So I am confused on how did this even boot up and work in the first place?. 

 

Thanks

 

 

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sstrell
Honored Contributor III
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1) You're getting the programming bitstream and processor code mixed up.  You must have a .pof or something in some non-volatile memory to program the device itself and then you need the Nios processor code stored somewhere else, pointed to by the reset vector, to start running that code when the processing starts (or is reset).

2) You're forgetting the CE signal.  And the 0x10000000 is the base address in the system design, not a physical address on the flash.  That goes back to the offset value to access the physical location on the flash.

3) No, starting location of code.

4) Your code is running directly from Eclipse (debug mode) over the JTAG connection.  Eventually, you have to put the code in flash (or wherever specified by the reset vector).

KellyJialin_Goh
Employee
2,737 Views

Hi MK,

Any updates from your side?


Regards,

Kelly


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MK_ABQ
New Contributor II
2,718 Views

Hello sstrell, Kelly,

Further questions from my side. 

 

"1) You're getting the programming bitstream and processor code mixed up.  You must have a .pof or something in some non-volatile memory to program the device itself and then you need the Nios processor code stored somewhere else, pointed to by the reset vector, to start running that code when the processing starts (or is reset)."

Q1) so let's say I have a .pof in some non-volatile memory, and the Nios CPU system design have chosen the reset vector memory as flash, then it's expected that the Nios processor code should be stored in the flash memory pointed by the reset vector offset address. Is my statement here, correct?

 

"2) You're forgetting the CE signal.  And the 0x10000000 is the base address in the system design, not a physical address on the flash.  That goes back to the offset value to access the physical location on the flash."

Q2) The base address in the qsys does not relate to the physical address on the flash, but the offset value relates to the actual physical address of the flash. Is this correct?. so, in my case, the expectation is there should be Nios processor code starting at 0x08b00000. Is this statement correct?

 

"Your code is running directly from Eclipse (debug mode) over the JTAG connection.  Eventually, you have to put the code in flash (or wherever specified by the reset vector)."

Q3) In this scenario I had actually mentioned the reset vector memory as flash. So, in the debug mode over JTAG, where was my Nios code stored? 

 

Q4) In the same scenario as Q3, once I change the offset address in the qsys for reset vector ( still retained the reset vector memory as flash),  and then run from eclipse in debug mode, I saw that the system was running fine and I was able to ping successfully  whenever I set the reset vector address in specific range, whereas in certain other reset vector address range, the eclipse debug mode could run only until auto negotiation, and ping could not proceed. So, it kind of got stuck. I could not understand this discrepancy and behavior. Any thoughts on this?

 

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sstrell
Honored Contributor III
2,700 Views

1) Yes.

2) Yes and yes.

3) Nowhere.  The code is sent over JTAG via the debugger.

4) No clue without knowing what your code is doing.

KellyJialin_Goh
Employee
2,694 Views

Hi,

I agree with sstrell's statement:

1)The Nios processor code will be stored in the flash memory pointed by the reset vector offset address

2)Nios processor code starts at 0x08b00000

3)The code is sent over JTAG via the debugger and not stored in any location


Thank you.

Regards,

Kelly


MK_ABQ
New Contributor II
2,681 Views

Thank you for clearing my doubts. The overall experiments I did have now boiled down to one final question from my side. 

 

I have a qsys project with NIOS, TSE IP, MSGDMA and other components in the system. The objective of the project is to bring up the TCP/IP stack and perform a ping from host pc to NIOS. Few pointers about the experiment.

1) The reset vector offset was pointed to external flash memory.

2) The FPGA was configured with .sof file. The flash was not programmed with anything from our side.  But the NIOS reset vector memory was chosen as flash and reset vector offset was pointed to a location in flash. 

3) The NIOS was booted in debug mode from eclipse over JTAG. 

4) The Eclipse project is a simple socket server template project from Intel.

 

The experiment turned out to be successful, but, with the following question that I still could not find a reasonable answer. 

 Q1) If the reset vector offset is set to be:  0x0000b020 in qsys, we can observe from Eclipse NIOS II console that auto negotiation is established, and ping is happening successfully.   But if I just change one single parameter in my entire project, which is the reset vector offset to be let's say: 0x08b00000 , then we can see only that auto negotiation is passed, but ping is not happening.  So, what direction would you think next? I understand it's difficult to give an answer without knowing what the code is doing. But I am just looking for a hypothesis, or possible scenarios on what could have caused this. Any inputs are welcome and would give me a new direction :).

 

Thank you

 

 

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KellyJialin_Goh
Employee
2,649 Views

Hi MK,

By changing the reset vector offset changes the location of the reset vector relative to the memory module’s base address and might affect your designed system.

Here is a link for your reference: https://www.intel.com/content/www/us/en/docs/programmable/683836/current/reset-vector.html


I am glad your project is compiled and pinged successfully with the correct base address.

Hope this clarifies your doubts.


Thank you.

Regards,

Kelly


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MK_ABQ
New Contributor II
2,645 Views

Hi Kelly,

In my scenario, I am using debugger option through JTAG to run NIOS. So as per the discussion so far and understanding, the NIOS code is stored nowhere and hence the reset vector offset  should not disrupt or affect the designed system in anyway. So I am not quite convinced with your statement. Am I missing something?

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KellyJialin_Goh
Employee
2,571 Views

Hi,

Sorry for misunderstanding. Yes, the NIOS code is stored nowhere and sent over JTAG via debugger.

Hope this clarifies your doubts. I will be setting this case to close pending in the next few days.


Thank you.

Regards,

Kelly


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MK_ABQ
New Contributor II
2,562 Views

Hi Kelly,

Thanks for your clarification. May I know what is the meaning of "setting this case to close pending"?. Does it mean I will have to wait for someone to address or give additional comments?

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KellyJialin_Goh
Employee
2,561 Views

Hi MK,

May I know what are the additional comments or clarification needed? Without looking at your code, I am not able to further give comments or support.

Close pending means I will not be able to support your queries after and the community will be there to help you with your further queries.


Thank you.

Regards,

Kelly


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