SDRAM Clock

[Altera_Forum]

Hi, 

I use SDRAM controller to connect FPGA and SPANSION(167 MHz) SDRAM. Nios II processor run up to 100 MHZ clock and I can not use higher frequency.   I did not use dedicated PLL FPGA pin for SDRAM clock.should I use dedicated PLL FPGA pin for SDRAM clock?  Regards

[Altera_Forum]

Usually you have to use a dedicated PLL output for sdram, not for a matter of different frequencies, but because the sdram clock needs to be phase shifted in order to meet the timing constraints.

[Altera_Forum]

Hi, 

I use -100 degree shift for SDRAM clock but my Nios II processor did not run.  Regards

[Altera_Forum]

-100 degree shift seems to me a high value. 

I look back to an old project with a Cyclone III device and 100MHz clock and I see I used -26 degrees.

[Altera_Forum]

I have seen cases where the SDRAM clock needs to lead nios clock by 3ns assuming Nios is running at 50MHz. Cris did you remember how you characterized the -26 degrees? Is there a formula for SDRAM delay calculation? or trial and error?

[Altera_Forum]

Look at the Embedded IP user guide 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_embedded_ip.pdf At page 2-10 you'll find the procedure for calculating the optimal sdram clock phase shift.

[Altera_Forum]

thanks Mr. Cris72. How can I use on_chip_memory for 140MHz clock? can I select different clock for processor and memory in the Nios System? 

Regards.

[Altera_Forum]

You can certainly select different clocks for processor, memory or whatever, but you need to add a clock crossing adapter between these system sections. 

This solution could be convenient if you have one or more devices with a smaller fmax than most of the others. But Nios and onchip memory are generally able to run at the same clock rate, so I think separate clocks is not the best option. Consider that clock crossing circuitry involves delays, data latencies and resource usage. So, running the whole system with a single clock, could possibly lead to better performance, although you have to use a lower clock frequency.

[Altera_Forum]

i remember some party said this is experimental value interm of the phase shirt and the delay number.. actually 100Mhz is also working.. you can double check with the memory test software example.