Signal Activities of Registered Nodes not from vcd, leading to Low Confidence power estimate

[taihai]

Hello,

I have recently synthesised my design in QuartusPro 21.3 targeting Agilex F-series and produced the .vo netlist file from EDA Netlist Writer, with 'simulation' tool name specified as VCS and language as Verilog. I then ran my testbench in VCS with`$dumpfile('file.vcd'); $dumpvars;` to produce the .vcd file which contains all the variables in top and submodules.

Now, with Power Analyzer settings configured with this .vcd and also default toggle rate for remaining signals as 12.5% (Thermal settings left as default), I obtained the attached Confidence Metric Details in QuartusPro. As shown in this screenshot, it shows that about 50.9% signal activities come from vcd, but 49% from Default Assignment, of which 78.1% are Registered. That means, of all the available registered nodes found in the netlist, signal activities of these 78.1% do NOT come from vcd.

But I am not sure why? Shouldn't VCS be able to measure the signal activities of these registered nodes, as it already identify the total number of registered nodes? But why QuartusPro thinks these should be Default Assignment instead?

My hope is that, solving my puzzle around Registered Nodes can help increase the Confidence Level of the power estimate by Power Analyzer. 

Best regards,

Taihai

[sstrell]

I don't think you can run a gate-level simulation on recent devices like Agilex, so you can't get a good .vcd from them for improving power analysis confidence.  What you created is probably based on an RTL sim I would guess.

[Farabi]

Hello, 

The way to get power estimates with high confidence is to use the toggle rate that comes from simulation or user-entered assignments. Refer to the "Confidence Metric Details" section in the link below,
https://www.intel.com/content/www/us/en/programmable/documentation/osq1513989409475.html

That being said, the way to tell the Power Analyzer Tool to use toggle rate from the simulation is with a vcd file. Here is a small guide to generate a vcd file in ModelSim,
https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd07062010_692.html

regards,
Farabi

[Farabi]

Hello, 

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

regards,
Farabi