Simple MAX 10 project with DDR3 UniPHY using HDL only

[emma97]

I want to implement a simple hdl design for the Arrow DECA. Most examples make use of other IP's like the Nios II Processor to control the DDR3 SDRAM. But I want to build my IP Variation and control it using VHDL or Verilog HDL only, thus, using the MegaWizard Plug-In, I configured MY_DDR3.v bassed on an example by the manufacturer (Terasic).

In my code (attached) I try to read and write simple data using simple buttons, a dip switch and a lcd to display my results. What I don't understand is why the wire "avl_ready", just won't turn on again after I do my write or read request.

Additionally, what I don't fully comprehend is the function avl_burstbegin, avl_be and avl_size. I think the "External Memory Interface Handbook Volume 3" is too advanced for me.

Thank you for your attention, I would like to hear your advice and I hope the best. Greetings.

[AdzimZM_Intel]

Hi Emma97,

I'm Adzim. Thank you for using Intel Community.

Did the design passed calibration?

If yes, then I think you should use a larger burst size such as 32 or 64.

You can refer to the Table 96. Local Interface Signals on "External Memory Interface Handbook Volume 3". I think the signals have been explained there.

The avl_burstbegin indicates when the burst operation will start.

You may read this document for better understanding: https://www.intel.com/content/www/us/en/docs/programmable/683091/20-1/burst-transfers.html

Thanks,

Adzim