Hello Forum,
What we are doing
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While fitting our logic, we are getting this error -
Error (170012): Fitter requires 108583 LABs to implement the design, but the device contains only 93312 LABs
QUESTION:
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Not able to corelate to why and where is it mentioned that 1SG280HU2F50E2VG device has93312 LABs and constitution of LABs and is it the issue with number of DSP blocks (100%), or what needs to be done in re-design in order to solve this fitter issue.
Any clue will be appreciated !!! OPTIMISATION is done for AREA.
Below is the fitter summary
+------------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------------+--------------------------------------------+
; Fitter Status ; Failed - Fri Feb 19 14:47:13 2021 ;
; Quartus Prime Version ; 18.0.0 Build 219 04/25/2018 SJ Pro Edition ;
; Revision Name ; CM4IKMCU_PERIPHERALS ;
; Top-level Entity Name ; top_mcu ;
; Family ; Stratix 10 ;
; Device ; 1SG280HU2F50E2VG ;
; Timing Models ; Preliminary ;
; Logic utilization (in ALMs) ; 645,479 / 933,120 ( 69 % ) ;
; Total dedicated logic registers ; 134940 ;
; Total pins ; 220 / 1,152 ( 19 % ) ;
; Total block memory bits ; 8,940,920 / 240,046,080 ( 4 % ) ;
; Total RAM Blocks ; 0 / 11,721 ( 0 % ) ;
; Total DSP Blocks ; 5,760 / 5,760 ( 100 % ) ;
; Total HSSI RX channels ; 0 / 96 ( 0 % ) ;
; Total HSSI TX channels ; 0 / 96 ( 0 % ) ;
; Total PLLs ; 2 / 152 ( 1 % ) ;
+---------------------------------+--------------------------------------------+
