System Library Properties

[Altera_Forum]

Hi, 

 I attached my System Library Properties and my .sopc file to the thread. When doing this, I have the following error : Downloading 00010020 ( 0%) Downloading 04000000 ( 2%) Downloaded 15KB in 0.3s (50.0KB/s)  Verifying 00010020 ( 0%) Verifying 04000000 ( 2%) Verify failed between address 0x4000000 and 0x400369F Leaving target processor paused  When putting everything (from program mem to stack mem) to onchip memory, my program works perfectly.  What did I do wrong ?  Myriam

[Altera_Forum]

it's related to SDRAM clock issues.

[Altera_Forum]

Hi, 

 Thank you for answering. I chose the followings : PLL clock frequency : 90MHz Memory clock frequency : 100MHz Local interface clock frequency : Full  On the slide PHY settings, I have a clock phase of 90. Then, I included the file ddr_sdram_phy_ddr_timing.sdc (which is generated by sopc if I'm not mistaken) to the project.  What should I change ?  Myriam  PS : I have a Cyclone III EP3C25

[Altera_Forum]

Hi Myriam, 

 I'm getting the same error and I'm stuck. If you find a solution let me know and I'll do the same. I need to resolve this soon. In the meantime I am going to try to come up to speed on the SignalTap II Logic Analyzer.

[Altera_Forum]

Most likely the sdram memory interface is either: 

1 - Not properly connected 2 - Not meeting timing (or your not giving Quartus the timing constraints).  Jake

[Altera_Forum]

--- Quote Start ---  Most likely the sdram memory interface is either: 1 - Not properly connected 2 - Not meeting timing (or your not giving Quartus the timing constraints).  Jake  --- Quote End ---    Thanks for the info Jake!  1 - Properly connected as far as I know. Using the CIII Starter Kit connections verified in the pin planner. SOPC compiled without errors. Quartus compiled without errors.  2a - Not meeting timing...What is the easiest way to check this. I am assuming that SignalTap II Logic Analyzer will be able to help me determine this so I need to come up to speed on that regardless but if there is another quicker way to determine which timing spec is not being met than please do let me know.  2b- Not giving Quartus the timing contraints...I assumed I gave these values correctly in the DDR SDRAM High Performance Controller Core added in SOPC. I selected the memory I was using and did not see any reason why I should change the default timing parameters. Attached is where I am assuming I am giving Quartus the timing constraints. How do you give Quartus the timing contraints?  I am also going to play around with the System Library Property settings.  I just love solving a good mystery. This stuff is fun. :)

[Altera_Forum]

Quartus needs a timing constraint file. This is kind of advanced stuff. Timing constraint files for Quartus have the extension ".sdc" (synopsys design constraints). The language is TCL. The SDC constraints are very specific to each design. However, if you've based your design on one of the starter kit example designs, it should have an SDC file that you can use as a basis. You can use multiple SDC files on a single project. 

Anyway, when you generated your SoPC system, it would have created an SDC file for the DDR interface.  So what you'll want to do in Quartus is: 1 - Assignments->Settings->Timing Analysis Settings. Select the "Use TimeQuest Timing Analyzer....." radio button. 2 - Then on the left hand side of the pane, click "TimeQuest Timing Analyzer" under the "Timing Analysis Settings" section. Here is where you specify the SDC files for the project. Now you'll want to make sure you've got the SDC file for the DDR controller added in there. So browse and look for something like "...._phy_timing.sdc" and add that file to the project. And as I've mentioned, depending on how much you've changed your design from the example, design, you may want to add the sdc file included in the example design.  Now when you compile your project in Quartus, the last step Quartus runs through is Timing Analysis. You can check the results to see if your design is meeting timing.  If you want to educate yourself on TimeQuest: http://www.altera.com/support/software/timequest/sof-qts-timequest.html  Jake

[Altera_Forum]

Thanks for taking the time to explain this Jake! 

 I'm adding to your rep because I appreciate it.