The regisers EN port issue

[MinzhiWang]

Hello guys,

There is one long regiser array implemented in my project, as following imgae:

Every register is realized to latch its closed ALUT output.

The FF primitive is called to implement above circuit, and the FF's enable port is uesed. The "enable" node is used to enable all resgisers. So this "enable" logic node is high fan-out node, as following image.

So I try to optimize this enable logic node by duplicating it to reduce its high fan-out. However, I will get following error in FIT stage when i apply this optimization. Along the register array, every LAB's first ALM will have this kind of error report.

Error(170208): Cannot place 4 nodes into a single ALM 
	Info(170017): Cannot place nodes in a single ALM -- the ALM would be illegal because Illegal ALE template cache hit 
	Info(170072): List of 4 nodes in the ALM 
		Info(170000): Node "SEP_QuadBLKs_Top_|u_TDC_QuadChs_Core|u3_tdc1ch_cc_dualregdualtdl|u_TDL_CC_DualReg_Topa|u_CarryChainDualRegInC10GX|gen[200].myffa|myff" 
			Info(170031): LE location constraint: Region lower-left corner: X91_Y8; Region upper-right corner: X91_Y8; Sublocation: 1 came from User Location Constraints 
		Info(170000): Node "SEP_QuadBLKs_Top_|u_TDC_QuadChs_Core|u3_tdc1ch_cc_dualregdualtdl|u_TDL_CC_DualReg_Topa|u_CarryChainDualRegInC10GX|gen[200].myffb|myff" 
			Info(170031): LE location constraint: Region lower-left corner: X91_Y8; Region upper-right corner: X91_Y8; Sublocation: 2 came from User Location Constraints 
		Info(170000): Node "SEP_QuadBLKs_Top_|u_TDC_QuadChs_Core|u3_tdc1ch_cc_dualregdualtdl|u_TDL_CC_DualReg_Topa|u_CarryChainDualRegInC10GX|gen[201].myffa|myff" 
			Info(170031): LE location constraint: Region lower-left corner: X91_Y8; Region upper-right corner: X91_Y8; Sublocation: 4 came from User Location Constraints 
		Info(170000): Node "SEP_QuadBLKs_Top_|u_TDC_QuadChs_Core|u3_tdc1ch_cc_dualregdualtdl|u_TDL_CC_DualReg_Topa|u_CarryChainDualRegInC10GX|gen[201].myffb|myff" 
			Info(170031): LE location constraint: Region lower-left corner: X91_Y8; Region upper-right corner: X91_Y8; Sublocation: 5 came from User Location Constraints

I just use different EN signals for the odd registers and even registers in that long register array. Why I will meet above error?

Thanks

[sstrell]

As it states, you are using some type of physical location constraint that prevents this type of tight fit now that you are duplicating the source register for the enable.  What do your constraints and code for this look like?

[MinzhiWang]

Hi sstrell,

The physical location constrains are applied to those registers before this error appear. The FF module is as following code:

 module primitive_ff (
 input wire s,
 input wire clk,
 input wire clr,
 input wire ena,
 output wire q
 );

 cyclone10gx_ff myff (
 .d(s),
 .clk(clk ),
 .clrn(),
 .aload(),
 .sclr(clr),
 .sload(),
 .asdata(),
 .ena(ena),
 .devclrn(),
 .devpor(),
 .q (q)
 );

 endmodule

If all 4 registers of single ALM use same enable signal, the project can pass thru full compilation. However, if odd and even use different enable signal the project can't pass thru Fit.

For the FF physical locaton constrains are as following:

set_location_assignment FF_X55_Y19_N1 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[20].myffa|myff"
set_location_assignment FF_X55_Y19_N4 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[21].myffa|myff"
set_location_assignment FF_X55_Y19_N7 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[22].myffa|myff"
set_location_assignment FF_X55_Y19_N10 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[23].myffa|myff"
set_location_assignment FF_X55_Y19_N13 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[24].myffa|myff"
set_location_assignment FF_X55_Y19_N16 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[25].myffa|myff"
set_location_assignment FF_X55_Y19_N19 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[26].myffa|myff"
set_location_assignment FF_X55_Y19_N22 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[27].myffa|myff"
set_location_assignment FF_X55_Y19_N25 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[28].myffa|myff"
set_location_assignment FF_X55_Y19_N28 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[29].myffa|myff"
set_location_assignment FF_X55_Y19_N31 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[30].myffa|myff"
set_location_assignment FF_X55_Y19_N34 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[31].myffa|myff"
set_location_assignment FF_X55_Y19_N37 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[32].myffa|myff"
set_location_assignment FF_X55_Y19_N40 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[33].myffa|myff"
set_location_assignment FF_X55_Y19_N43 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[34].myffa|myff"
set_location_assignment FF_X55_Y19_N46 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[35].myffa|myff"
set_location_assignment FF_X55_Y19_N49 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[36].myffa|myff"
set_location_assignment FF_X55_Y19_N52 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[37].myffa|myff"
set_location_assignment FF_X55_Y19_N55 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[38].myffa|myff"
set_location_assignment FF_X55_Y19_N58 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[39].myffa|myff"

set_location_assignment FF_X55_Y19_N2 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[20].myffb|myff"
set_location_assignment FF_X55_Y19_N5 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[21].myffb|myff"
set_location_assignment FF_X55_Y19_N8 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[22].myffb|myff"
set_location_assignment FF_X55_Y19_N11 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[23].myffb|myff"
set_location_assignment FF_X55_Y19_N14 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[24].myffb|myff"
set_location_assignment FF_X55_Y19_N17 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[25].myffb|myff"
set_location_assignment FF_X55_Y19_N20 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[26].myffb|myff"
set_location_assignment FF_X55_Y19_N23 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[27].myffb|myff"
set_location_assignment FF_X55_Y19_N26 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[28].myffb|myff"
set_location_assignment FF_X55_Y19_N29 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[29].myffb|myff"
set_location_assignment FF_X55_Y19_N32 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[30].myffb|myff"
set_location_assignment FF_X55_Y19_N35 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[31].myffb|myff"
set_location_assignment FF_X55_Y19_N38 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[32].myffb|myff"
set_location_assignment FF_X55_Y19_N41 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[33].myffb|myff"
set_location_assignment FF_X55_Y19_N44 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[34].myffb|myff"
set_location_assignment FF_X55_Y19_N47 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[35].myffb|myff"
set_location_assignment FF_X55_Y19_N50 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[36].myffb|myff"
set_location_assignment FF_X55_Y19_N53 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[37].myffb|myff"
set_location_assignment FF_X55_Y19_N56 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[38].myffb|myff"
set_location_assignment FF_X55_Y19_N59 -to "inst3|u_TDL_CC_DualReg_Top|u_CarryChainDualRegInC10GX|gen[39].myffb|myff"

As above constrains, all single LAB's 40 registers are constrain to corresponding logic nodes. They are grouped to two sets. One is myffa, another one is myffb. If both myffa and myffb use same enable signal, the project can pass thru full compliation. When myffa use ENa and myffb use ENb the project can't pass FIT stage and get the errors presented as the first post.

BTW, enable is generated as :

enable <= ena or enb;

So enable just merger ena and enb. I doubt that the registers inside same LAB can only use same single enable port?

[FvM · Accepted solution]

Hi,
the problem might be explained by Cyclone 10 GX device handbook,  Figure 7. ALM Connection Details for Intel Cyclone 10 GX Devices

It shows that clock selection (and also clock enable selection, because clock and enable are tied) for adjacent registers isn't independent. There are two muxes for four registers.

Regards

Frank

[MinzhiWang]

Hello FvM,

Thanks for you reply.

[WeiHanT_Intel]

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