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HI! Everyoe!
I want to use pll to generate two clocks, one is clk_100m,and the other is clk_25m, After compilation,there is a warning: warning: PLL ""pll:pll_inst|altpll:altpll_component|pll" output port [1] feeds output pin "clk_25m" via non-dedicated routing--jittter performance depends on switching rate of other design elements.Use pll dedicated outputs to ensure jitter performance. I have not assigned pins(for I don't have a board), So I want to know if the warning still exist after the dedicated pins have been assigned??Link Copied
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The PLL's have dedicated output ports called PLL_CLKOUT. If you take a PLL clock and drive it directly to one of these ports, it will bypass the global clock tree and go directly out, resulting in the least amount of jitter and the warning should go away.
That being said, I have never heard of a clock that didn't work by not going out a regular I/O. A good example is source-synchronous interfaces that transmit the clock with the data. Those work by having the clock go out a regular I/O instead of the PLL_CLKOUT(so the clock and data delays match), and can pass data extremely high rates(say 800Mbps+). The 533MHz DDRs, whose data rate is twice that, does not use the PLL_CLKOUT. My point is that, if you're just using it to create an off chip clock, the PLL_CLKOUT is great, but I think the warning is often interpreted too severely, as many, many designs use regular I/O to send clocks out without problem.- Mark as New
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Thanks for your reply,Rysc!
and I have a new queston,after compilation,there is a such warning: warning:clock latency analysis for pll offsets is supported for the current device family,but is not enabled. Now, can you tell me what should I do to avoid the warning ?- Mark as New
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Are you using Classic Timing Analyzer? If I remember, that's a setting under Assignents -> Settings -> Timing Analyzer -> More Settings. You can go there and turn it on. If you use TimeQuest, it's automatic.
(I don't remember what this option does though...)
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