Transceiver CDR Question

[Altera_Forum]

Hi 

 I want build a design where the FPGA will be receiving 10-bit serial data using one XCVR and a separate clock is provided which corresponds to the 10-bit parallel clock (e.g. 100 MHz clock for 1Gbps serial data stream). So the clock is not embedded in the data stream. However, I need to be able to handle the input data rate changing (e.g. 100 MHz clock with 1Gbps data --> 150 MHz clock with 1.5Gbps data or some other clock & data rate; serialization factor is always 10). Assume FPGA is Cyclone/Arria V.  I am new designing with XCVR. Here are my questions:  - For the PMA block, assuming I set it up for 10:1 deserialization, what Rx data rate should I set in the XCVR PHY megawizard GUI - is it the max expected data rate? - I plan to connect the slow clock provided along with the data to the "refclk" input of the CDR. Does the CDR PLL automatically readjust its serial clock output (serial clock = 10x of slow clock) when the slow clock input frequency changes? I am wondering if I need a XCVR reconfiguration controller to manipulate the CDR for this situation? - When is XCVR reconfiguration actually needed? - Also, should I use the CDR in LTR (lock-to-refclk) or LTD (lock-to-data) mode for my application where the clock/data rate change? Or simply leave it auto mode?  I would have used the LVDS SERDES block but its supported data rate is not good enough for my application.  Appreciate your feedback!

[Altera_Forum]

- For the PMA block, assuming I set it up for 10:1 deserialization, what Rx data rate should I set in the XCVR PHY megawizard GUI - is it the max expected data rate? 

  Hi,  The RX data rate should be set to the data rate that you are operating the link? For example, 1G or 1.5G. If not, the RX would not be able to recover the right data.

[Altera_Forum]

- I plan to connect the slow clock provided along with the data to the "refclk" input of the CDR. Does the CDR PLL automatically readjust its serial clock output (serial clock = 10x of slow clock) when the slow clock input frequency changes? I am wondering if I need a XCVR reconfiguration controller to manipulate the CDR for this situation? 

- When is XCVR reconfiguration actually needed?  Hi, Whenever the refclk changes, you should perform dynamic reconfiguration to the CDR so that the internal counters can be updated to work with the new data rate. If not, you might get incorrect data recovered from the CDR. The XCVR reconfiguration controller is required to performed dynamic reconfiguration.

[Altera_Forum]

So you recommend using a reconfig controller for XCVR because the refclk frequency could change. Do you have any recommendation of how I could detect the refclk frequency change? I will not get this info (i.e. no separate signals available) from the transmitting side. 

 BTW, when the refclk changes, I assumed the PLL inside the CDR block would simply lose lock and with a reset, it would gain a lock again. Is this not true?

[Altera_Forum]

"So you recommend using a reconfig controller for XCVR because the refclk frequency could change. Do you have any recommendation of how I could detect the refclk frequency change? I will not get this info (i.e. no separate signals available) from the transmitting side." 

 Yes you are right. You would need the reconfig controller to perform Channel and CDR reconfiguration. One thing that you should take note is that, in V generation devices, even though you are not using any reconfiguration feature, it is still mandatory to connect the reconfig controller to the PHY IP. This is for the offset cancellation to run properly.

[Altera_Forum]

"BTW, when the refclk changes, I assumed the PLL inside the CDR block would simply lose lock and with a reset, it would gain a lock again. Is this not true? " 

 The CDR should lose lock to data. But I am not sure if it will lose lock to refclk or not. It is advisable to reset the CDR after reconfiguring it.

[Altera_Forum]

With regard to the CDR reconfiguration, which specific parameters need reconfiguration? I'm assuming it's the channel PLL settings in my case since the input refclk to CDR can change on the fly. Where are these settings listed and how do I figure out what new settings to apply for each different refclk freq (e.g. ranging from 650MHz to 3GHz)?

[Altera_Forum]

Hi, 

 For CDR dynamic reconfiguration, it is recommended for you to use to MIF file to reconfigure the CDR. Quartus II will generate one MIF for each transceiver configuration after successful compilation.

[Altera_Forum]

Just to clarify, when I generate the XCVR related blocks (PHY, PLL, etc.) thru Magawizard, the MIF is not generated then? I would need to do a full design compilation to get the MIF files?

[Altera_Forum]

--- Quote Start ---  Just to clarify, when I generate the XCVR related blocks (PHY, PLL, etc.) thru Magawizard, the MIF is not generated then? I would need to do a full design compilation to get the MIF files?  --- Quote End ---    The MIF files are generated after Assembler compilation stage. They are not generated when you instantiate through Megawizard.

[Altera_Forum]

--- Quote Start ---  Just to clarify, when I generate the XCVR related blocks (PHY, PLL, etc.) thru Magawizard, the MIF is not generated then? I would need to do a full design compilation to get the MIF files?  --- Quote End ---    After successful compilation, you can look into the reconfig_mif folder in the project directory. You can refer to Altera Transceiver PHY IP Core User Guide -> "MIF Generation" section for further info.