Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Treminating LVDS outputs

PDone
New Contributor I
286 Views

I am using a Cyclone V which interfaces without to other boards in our system using LVDS ports.  In some system configurations these LVDS inputs and outputs are hooked up, in others they are left open.

Do I need to terminate the LVDS when the IO lines are open?

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EngWei_O_Intel
Employee
264 Views

Hi Peter Donegan

Sorry for late response due to long holiday here. 

For open connection, you can refer to pin connection guideline below for proper handling:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-v/pcg-01014.pdf 

 

Thanks.

Eng Wei

EngWei_O_Intel
Employee
241 Views

Hi Peter Donegan

 

We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Eng Wei

 

 

PDone
New Contributor I
229 Views
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