Using the BITEC daughterboard with Cyclone IV dev board

[Altera_Forum]

hi,  

 I'm using the Cyclone IV development board with the BITEC Quad Video daughter board. What I'm trying to do is receive a composite video input stream from the BITEC QV board, so that this video stream is processed on the Cyclone IV development board, before it's transmitted to the DVI output on the BITEC QV board.   Previously, I was able to create a design (based on the "hsmc_mosaic_example_design_3c120_v81") that works with the Cyclone III development board, using the HSMC port B. When trying to port this design to the Cyclone IV development board (still using HSMC port B ), I found that the I2C lines SDA and SCL on the BITEC QV board are not routed to the FPGA. I then switched to using the HSMC port A on the Cyclone IV development board, doing so I was able to communicate with the BITEC QV board using I2C.   The problem I'm having now is that the DVI output clock (BITEC_QV_IDCKp), which is using the LVDS IO_STANDARD is placed so that it's in conflict with the 1.st and 3.rd bits of the video input signal and I'm getting the following error messages :   Error (169079): Pad 314 of non-differential I/O pin 'BITEC_QV_CH1_IN_D[3]' in pin location M21 is too close to pad 310 of differential I/O pin 'BITEC_QV_IDCKp' in pin location P21 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug. Error (169079): Pad 314 of non-differential I/O pin 'BITEC_QV_CH1_IN_D[3]' in pin location M21 is too close to pad 309 of differential I/O pin 'BITEC_QV_IDCKp(n)' in pin location N21 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug. Error (169079): Pad 313 of non-differential I/O pin 'BITEC_QV_CH1_IN_D[1]' in pin location M22 is too close to pad 309 of differential I/O pin 'BITEC_QV_IDCKp(n)' in pin location N21 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug. Error (169079): Pad 313 of non-differential I/O pin 'BITEC_QV_CH1_IN_D[1]' in pin location M22 is too close to pad 310 of differential I/O pin 'BITEC_QV_IDCKp' in pin location P21 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.   I found a possible solution in the quartus help :   http://quartushelp.altera.com/11.1/mergedprojects/msgs/msgs/efiomgr_io_close_to_lvds.htm   However, I don't have the option to assign one of the conflicting I/O pins to a different location, so now I'm wondering if there is another solution to the problem ?