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VHDL ATTRIBUTE ram_init_file ignored

WalterGallegos
Beginner
1,062 Views

To workaround Qaurtus unsuported VHDL constructions; I write

 

...

SIGNAL LocalRAM : LocalRAMDesc;

ATTRIBUTE ram_init_file : string;

ATTRIBUTE ram_init_file OF LocalRAM : SIGNAL IS "TestInt.mif";

...

 

Quartus RAM summary

 

RAM Summary report for MCU201923

Tue Jun 18 10:46:09 2019

Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition

 

 

---------------------

; Table of Contents ;

---------------------

 1. Legal Notice

 2. Analysis & Synthesis RAM Summary

 

 

 

----------------

; Legal Notice ;

----------------

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(including device programming or simulation files), and any

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refer to the applicable agreement for further details, at

https://fpgasoftware.intel.com/eula.

 

 

 

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

; Analysis & Synthesis RAM Summary                                                                                                                                                    ;

+---------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+

; Name                                                                           ; Type ; Mode            ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;

+---------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+

; LRAM:A2|altsyncram:LocalRAM[0][15]__3|altsyncram_5q71:auto_generated|ALTSYNCRAM ; AUTO ; Single Port     ; 4096        ; 8           ; --          ; --          ; 32768 ; None ;

; LRAM:A2|altsyncram:LocalRAM[0][15]__7|altsyncram_2eg1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 4096        ; 8           ; 4096        ; 8           ; 32768 ; None ;

; LRAM:A2|altsyncram:LocalRAM[0][23]__2|altsyncram_5q71:auto_generated|ALTSYNCRAM ; AUTO ; Single Port     ; 4096        ; 8           ; --          ; --          ; 32768 ; None ;

; LRAM:A2|altsyncram:LocalRAM[0][23]__6|altsyncram_2eg1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 4096        ; 8           ; 4096        ; 8           ; 32768 ; None ;

; LRAM:A2|altsyncram:LocalRAM[0][31]__1|altsyncram_5q71:auto_generated|ALTSYNCRAM ; AUTO ; Single Port     ; 4096        ; 8           ; --          ; --          ; 32768 ; None ;

; LRAM:A2|altsyncram:LocalRAM[0][31]__5|altsyncram_2eg1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 4096        ; 8           ; 4096        ; 8           ; 32768 ; None ;

; LRAM:A2|altsyncram:LocalRAM[0][7]__4|altsyncram_5q71:auto_generated|ALTSYNCRAM ; AUTO ; Single Port     ; 4096        ; 8           ; --          ; --          ; 32768 ; None ;

; LRAM:A2|altsyncram:LocalRAM[0][7]__8|altsyncram_2eg1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 4096        ; 8           ; 4096        ; 8           ; 32768 ; None ;

+---------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+

 

Check at MIF column None.

 

Comments ?

 

 

 

 

 

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JoanneSinY_L_Intel
749 Views

Hi,

 

Can you share a simple design that we can use to duplicate the error above?

 

Thanks

Joanne

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