Variable transceiver bitrate on a Cyclone V GX FPGA

[arno_va]

We're building a custom transceiver application where we only use the transceiver's TX output. The FPGA's reference clock is clocked externally with a fixed 50 MHz clock for clocking the FPGA's transceiver. We need to be able to dynamically change the transceiver's TX bit/clock rate (during run-time, without recompiling) to arbitrary values (to anything between 1-1000 MBps, so we can't use clock-switching). I've read all the relevant documentation I could find but it's unclear to me whether this can be performed completely on-chip using eg. one of the FPGA's PLLs or that is only possible using an external PLL/synthesizer IC which clocks the FPGA's reference clock. If I've understand it correctly you can't use transceiver-reconfigure for this, right?

Any help or pointers are highly appreciated.

[FvM]

Hi,
first step would be to clarify your specification based on Cyclone V GX datasheet.

You talk about transceivers, but they don't support data rate below 600 MBPS. So you either need to switch between regular SERDES and transceivers to cover the speed range. Or use special oversampling solutions.

Also, did you read about PLL reconfiguration? 

[arno_va]

Yes I'm aware it can't go any lower than 600 MBPs. Most important thing for us now is that it at least can be set anywhere between 600 and 1000 MBPs (with 1MBP increments). Yes I read about PLL reconfiguration, but it's totally unclear to me whether this is possible when used with a transceiver, and if so: how? I couldn't find any documentation, or even better examples on how to accomplish that.

[arno_va]

Anyone that can provide some more pointers/info for my issue?

[AqidAyman_Intel]

Have you check on the dynamic reconfiguration?

You can read about dynamic reconfiguration in the V-Series Transceiver PHY IP Core User Guide:

https://www.intel.com/content/www/us/en/docs/programmable/683171/current/native-transceiver-phys.html

[AqidAyman_Intel]

Apologies for the wrong link. You can check link below:

https://www.intel.com/content/www/us/en/docs/programmable/683171/current/transceiver-reconfiguration-controller-64716.html

[AqidAyman_Intel]

Hi,

Do you have any more concern on this issue?

[arno_va]

Yes, my problem isn't fixed yet. I think transceiver reconfig doesn't satisfy my needs. I really need to be able to dynamically change the bitrate from 600 to 1000 MBps. So the question remains: can this somehow all be done in the fpga (using an additional PLL driving the transceiver's PLL?) or do I need an external PLL/clock synthesizer for this?

[AqidAyman_Intel · Accepted solution]

This is what feedback that I got from the internal team that I think worth to share with you:

"If you adjust the REFCLK input to the Tx PLL, you'll maintain lock for some of the time, but the PLL settings may eventually become sub-optimal. Each data rate has a specific set of PLL settings. 600Mbps may not be the same as 1Gbps. One method you can investigate is to generate a MIF file for 600mpbs and another for 1Gbps. if the two are identical, you might be able to adjust the REFCLK input. However, we don't recommend PLL cascading for XCVR interfaces due to jitter concerns caused by core noise. Having said that, 1Gbps is pretty slow so jitter is less critical, it depends on the protocol requirements."

Regards,

Aqid