Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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We need to keep the overall latency from FPGA request to memory device and back to FPGA at a minimum. We have come across a situation that a 1SG280HU2F50E2VGS1 device works and a 1SM21BHU2F53E2VGS1 device does not.

MBaum8
Beginner
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Nooraini_Y_Intel
Employee
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Hi,

 

Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign/find someone to assist you. Thank you.

 

Regards,

Nooraini

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