Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21088 Discussions

We need to keep the overall latency from FPGA request to memory device and back to FPGA at a minimum. We have come across a situation that a 1SG280HU2F50E2VGS1 device works and a 1SM21BHU2F53E2VGS1 device does not.

MBaum8
Beginner
‎01-14-2019 11:30 PM
1,273 Views
 
0 Kudos

Link Copied

1 Reply
Nooraini_Y_Intel
Employee
‎01-28-2019 05:55 AM
471 Views

Hi,

 

Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign/find someone to assist you. Thank you.

 

Regards,

Nooraini

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.