I am working on a baremetal design in which 4 on-chip Memory(RAM) should be connected to the HPS (Arria 10 HPS). I use memory IPs available in Qsys and connect them to h2f_axi_master. The memories are 32 bit width of the size 4096 bytes. The problem is that when I write ,for instance, on second memory after a certain address the first memory is also written, or sometimes, by re designing the qsys, while writing the second memory the first memory is written simultaneously until a certain memory location. To be more clear, all memory base addresses are automatically generated using the Quartus scripts, and they are added to H2f bridge address to get the exact physical addresses.I tried several approaches such as; using Pipeline bridge, re-configuring the bootloader. putting "nop" between consecutive memory writes, and probing,via signal tap, the Avalon signals; which indicates undesirable high value on first memory while the second memory is supposed to be written. What is the problem? should I use any particular bridge or arbiter?
If each memory has its own unique base address and is not overlapping with any others in the H2F master's address space (and Qsys won't let you generate if they do), I'm not sure how this would be happening.What signal on the first memory has an "undesirable high value" when writing to the second?
The problem solved. I rechecked all the addresses, then I got, as I use integer data type and memories are built by 32bit cells, My C program violates the last address of each memory blocks, hence something like address overflow! So I should have divided each address span of memory blocks by 4 in order to find the last addressable locations. All in C code.