Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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baseAddress is 0x00000000?

tommmy
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regmap file generated by platform designer has these contents <baseAddress>0x0000000</baseAddress>

i think it is not right, baseAddres should be generated with real peripheral base address

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sstrell
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No, base addresses are either manually set by you or you can use the option from the system menu to have base addresses assigned automatically in non-overlapping ranges.  The addressing of registers or memory locations within a component are offsets from the base address set in Platform Designer.

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tommmy
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you did not got it .  "*.regmap" file is generated after you set the component base address use platform designer and click the generate button. you can set address range manually or use auto address assignment, but i am not talk about how to set base address.

regmap file is generated by *.svd file specified by

```set_interface_property [interface name] CMSIS_SVD_FILE [svd file path]```

in *_hw.tcl

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ShengN_Intel
직원
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Hi,


Any further update?


Thanks,

Best Regards,

Sheng


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ShengN_Intel
직원
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Hi,


Check this https://www.intel.com/content/www/us/en/docs/programmable/683609/23-1/files-generated-for-systems.html

The .regmap file describes the register map information of host and agent interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. 

The <baseAddress>0x0000000</baseAddress> you found in .regmap file complements with the for example &lt;name&gt;altera_avalon_pio&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; in .sopcinfo.

I think the baseAddress you're looking for is the one in .sopcinfo for example like below:

<isBridge>false</isBridge>

<moduleName>led_0</moduleName>

<slaveName>s1</slaveName>

<name>led_0.s1</name>

<baseAddress>32</baseAddress>

<span>16</span>


Thanks,

Best Regards,

Sheng


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tommmy
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I had read these docs before, and  i am sure the baseAddress in the generated .regmap file is  0x00000000, the baseAddress should be substituded with real base address of every avalon-mm interface during generating. the .regmap can be used for nios2 software debugging, but if the baseAddress is not right, this file would be useless.

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sstrell
명예로운 기여자 III
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So you're saying that all the components' base addresses in this file are 0x0 even though you've set base addresses in Platform Designer correctly?  You should also look in the .sopcinfo file.  That's the main file for software build tools.  If that file is correct and .regmap is not, that's very strange.

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tommmy
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yep, the.sopcinfo file is correct, but the generated .regmap file is not. 

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ShengN_Intel
직원
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Hi,


Usually nios2 software build rely on .sopcinfo file. Or may be you can further confirm by opening a new thread in this forum https://community.intel.com/t5/Nios-II-Embedded-Design-Suite/bd-p/nios-II-embedded-design-suite


Thanks,

Best Regards,

Sheng


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tommmy
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ShengN_Intel
직원
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Hi tommy,


I'll ask platform designer related expert and let you know the update or feedback.


Thanks,

Sheng


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ShengN_Intel
직원
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Hi tommy,


Still waiting for expert reply. Will come back to you soon there's any further update.


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ShengN_Intel
직원
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Hi tommy,


Still waiting for expert response. Will come back to you soon there's any further update.


Thanks,

Best Regards,

Sheng


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