Programmable Devices

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Programmable Devices

Discussions

Transceiver placement issue

Data Mask Pins for Cyclone III DDR2 Interface

DDR2 Altmemphy Read and write through Nios

Stratix V QDR-II+ Controller PLL won't lock

Cyclone V Triple Speed Ethernet in Quartus 13.1

SoC Dev Kit Quality of Experience Survey

Cyclone III EP3C25 - Pin 141 can't drive signal ?

Cyclone IV EP4CE15 FPGA JTAG programming issue

Compatibility of compiled design.

strange behavior of DCFIFO, how to meet the "Functional Timing Requirements"

SDI with Clocked Video In/Out - How to go from 10 bits to 8 bits color depth???

Hard emi, Cyclone V SX, max speed

CycloneIV adder behavior

timing problem 1

TimeQuest User Guide Question

Featured Content

Agilex 3 GTS PCIe IP missing

Issue with Pixel Buffer DMA AVMM -> AXI connection on DE25-Standard (Agilex5)

Quartus 25.1.1 Pro Fitter Error with Agilex3

Re: LVDS pin detail on Arria 10

Re: Download speed