Programmable Devices

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Programmable Devices

Discussions

Cyclone V - How to split DDR3 memory for HPS and FPGA?

How to optimize the CPLD logic gates or blocks consumption?

EPCS16 configures Cyclone III, but EPCQ16 in ASx1 mode doesn't

Distributing low frequency clock with Cyclone V FPGA

no element generate when compiled

Cyclone V Hard IP support for PCIe, GigE and Serial Rapid IO

Compile problems of altera sample application

Multi Touch LCD Interface with Arrow SoCKit

I want Max 10 Handbook for project.

Has anyone successfully inferred read enable ports on true dual-port ram?

Wire assignment in verilog

New user. Best forum for MAX 7000 and MAX+ questions?

beginners question: MAX V capacity needed for simple glue logic

error when Debag Cycline M SoC in DS-5

skbuff: skb_over_panic on Cyclone V: SoC ARM (SocKit) board

Featured Content

AGILEX5 - HPS-first - timeout waiting for RECONFIG_COMPLETED

10M04SCU324I7G - I/O timing

SDI pinning on Agilex 5

I350 igb driver failed with error -2

Request for the Product Lifecycle Status

Re: USB Blaster selection criteria

Solution: USB Blaster Driver for Windows 11 ARM

Re: MAX10 (Select Internal Configuration mode with ERAM )