can't see enough FMAX

[Altera_Forum]

hello 

 I create one FPGA project with CycloneV( 5CGXFC9E6F35C7 ). it has 80 pairs of LVDS inputs as DDRIO input.  when I compile the project, it says FMAX is 103MHz that is too slower than I expected. I need 300MHz.  I tried to compile each 8bits LVDS inputs independently.  then I found that some of them is 260MHz FMAX ( that still not enough by the way. ) the other hand, some other is 103MHz FMAX.  why LVDS input has different FMAX? I mean this big difference.  do I miss something?  thank you.

[Altera_Forum]

What do your SDC timing constraints look like? How is your clocking set up in your design. More details needed here.

[Altera_Forum]

hello sstrell. 

thanks for your answer.  actually, I do not know SDC file well. I just wrote those.  for 300 MHz clock is this. create_clock -name {lvdsclk300} -period 3.333 -waveform { 0.000 1.666 } [get_ports {cam_clk[3]}]  and also for delay, I wrote this statement for pins cam_data[0] to cam_data[79] set_input_delay -add_delay -clock [get_clocks {lvdsclk300}] 0.000 [get_ports {cam_data[0]}]