can two emif ipcores share bank?

[allen18]

Hi :

    I will use two 16bit ddr4 controller, the readme.txt file show a example  I/O assignments, if this one controller  will occupy two banks, total 4 banks.  Two controllers working at same frequency,  I want to connect PLL reference clock signal from bank 3J to two pll_ref_clk of controller instances in top.v file, and place some DQ signals of two controllers in bank 3K,  place addr and command signals of two controllers in bank 3J and 3L. So, I can place two controllers in total 3 banks. I'm not sure if it's possible to do this ？

[sstrell]

You don't mention the target device which is absolutely key in determining whether this is possible.

In Agilex 7, this is not possible.

In Stratix 10, Arria 10, and Cyclone 10, this would be possible though the data pins would need to be split for each interface between the "outer" bank and the center bank (8 in 3L and 8 in 3K, for example).

[allen18]

Hi, The device is stratix10 1SX110HN2F43I2VG, I plan to use the hard DDR controllers in bank 3L and 3J. For the first controller, I will place the address and command signals in bank 3L, and place 8 DQ signals in bank 3L. The remaining 8 DQ signals placed in bank 3K. For the second controller, I will place the address and command signals in bank 3J, and place 8 DQ signals in bank 3J. The remaining 8 DQ signals will also be placed in bank 3K. Both controllers will share the same reference clock input.Full compilation was successful but I am worried about the practical feasibility of it.

[sstrell · Accepted solution]

This is how resource sharing for EMIFs is supposed to be set up and work, so you shouldn't have an issue.

https://www.intel.com/content/www/us/en/docs/programmable/683741/22-3-19-2-5/resource-sharing-guidelines-multiple-01.html

[allen18]

Thank you, I didn't read this documentation carefully before.It should be feasible.