Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
The Intel sign-in experience has changed to support enhanced security controls. If you sign in, click here for more information.
19984 Discussions

configurate altlvds_rx input port rx_syncclock for cyclone iv

XQSHEN
Novice
577 Views

EP4CE22F17C7

The ip user guide, we can see input port rx_syncclock for this ip altlvds_rx.

But I can not see anywhere from quartus prime 18.0.

0 Kudos
9 Replies
AminT_Intel
Employee
560 Views

Hello,


Can you share which part of the document do you mean?


Thank you.


XQSHEN
Novice
550 Views
XQSHEN
Novice
548 Views

I don't see anywhere from below window to configure  rx_syncclock or rx_cloreclk.

So the code generated doesn't have this port for me to do anything.

XQSHEN_0-1651189421685.png

XQSHEN_1-1651189517936.png

 

 

XQSHEN
Novice
542 Views

I suppose there should be somewhere can pull out rx_syncclock or rx_cloreclk.

Then we can use it my project and connect to external pll output.

Unfortunately, I don't find it.  I need this help.

XQSHEN
Novice
518 Views

How to enable below rx_coreclk?

 

XQSHEN_0-1651308439426.jpeg

 

AminT_Intel
Employee
463 Views

Hello,


Which version of Quartus and device do you use?


Thank you.


XIAOQ
Beginner
443 Views

EP4CE22F17C7

 

quartus prime 18.0.

AminT_Intel
Employee
429 Views

Hello,


This option is enabled when the LVDS is implemented in logic. When you turn on this option, it adds an input port, which when asserted performs an asynchronous reset of all the logic in the ALTLVDS_RX IP core excluding the PLL.


Thank you.


AminT_Intel
Employee
413 Views

 We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Reply