configurate altlvds_rx input port rx_syncclock for cyclone iv

[XQSHEN]

EP4CE22F17C7

The ip user guide, we can see input port rx_syncclock for this ip altlvds_rx.

But I can not see anywhere from quartus prime 18.0.

[AminT_Intel]

Hello,

Can you share which part of the document do you mean?

Thank you.

[XQSHEN]

Please refer to 

Solved: altlvds_rx - Intel Communities

[XQSHEN]

I don't see anywhere from below window to configure  rx_syncclock or rx_cloreclk.

So the code generated doesn't have this port for me to do anything.

[XQSHEN]

I suppose there should be somewhere can pull out rx_syncclock or rx_cloreclk.

Then we can use it my project and connect to external pll output.

Unfortunately, I don't find it.  I need this help.

[XQSHEN]

How to enable below rx_coreclk?

[AminT_Intel]

Hello,

Which version of Quartus and device do you use?

Thank you.

[XIAOQ]

EP4CE22F17C7

quartus prime 18.0.

[AminT_Intel]

Hello,

This option is enabled when the LVDS is implemented in logic. When you turn on this option, it adds an input port, which when asserted performs an asynchronous reset of all the logic in the ALTLVDS_RX IP core excluding the PLL.

Thank you.

[AminT_Intel]

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