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configurate altlvds_rx input port rx_syncclock for cyclone iv

XQSHEN
Novice
1,264 Views

EP4CE22F17C7

The ip user guide, we can see input port rx_syncclock for this ip altlvds_rx.

But I can not see anywhere from quartus prime 18.0.

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AminT_Intel
Employee
1,247 Views

Hello,


Can you share which part of the document do you mean?


Thank you.


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XQSHEN
Novice
1,237 Views
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XQSHEN
Novice
1,235 Views

I don't see anywhere from below window to configure  rx_syncclock or rx_cloreclk.

So the code generated doesn't have this port for me to do anything.

XQSHEN_0-1651189421685.png

XQSHEN_1-1651189517936.png

 

 

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XQSHEN
Novice
1,229 Views

I suppose there should be somewhere can pull out rx_syncclock or rx_cloreclk.

Then we can use it my project and connect to external pll output.

Unfortunately, I don't find it.  I need this help.

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XQSHEN
Novice
1,205 Views

How to enable below rx_coreclk?

 

XQSHEN_0-1651308439426.jpeg

 

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AminT_Intel
Employee
1,150 Views

Hello,


Which version of Quartus and device do you use?


Thank you.


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XIAOQ
Beginner
1,130 Views

EP4CE22F17C7

 

quartus prime 18.0.

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AminT_Intel
Employee
1,116 Views

Hello,


This option is enabled when the LVDS is implemented in logic. When you turn on this option, it adds an input port, which when asserted performs an asynchronous reset of all the logic in the ALTLVDS_RX IP core excluding the PLL.


Thank you.


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AminT_Intel
Employee
1,100 Views

 We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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