cyglone 5 gt interface for ads5263

[Altera_Forum]

Hello. 

Is there a ready block to connect the cyclone_gt to the adc ads5263? The device ads5263 have 4 channels analog input, and each channel has 2 ddr lvds outputs lanes.  then i have: 1 bitclock wire (ddr) 1 frameclock wire. 2 lvds lines for each channel.  Can i use alt_ddio or alt_lvds_rx megafunctions?  Regards, Luca

[Altera_Forum]

Ok, after a week i have resolved. 

The ads5263 is now ready. I use 8 channels alt_lvds_rx at 800 Mbps, for implement 4 channels 16 bit at 100Msps I do not use frame clock, but the bit align function of serdes. Best regards, Luca

[Altera_Forum]

I'm also working with ADS5263 just now. What kind of board do you use? I mean is it your custom board or evaluation? I had some problems with LVDS termination. I used 100 Ohms external resistors for LVDS differetial termination and noticed that AC amplitude between positive and negative lines on bit clock line is differente: 270 mV and 600 mV respectively. Furthermore when board's temperature went high, amplitudes went low and PLL unlocked on 40-50 C degrees. The sitaution becomes better after I soldered resitors out of the board and enabled on-chip differential terminator. And one more quastion about synchronization. Do you use PLL dynamic phase shift? If so what clock are you shift 800 MHz, 100 MHz (enable) or 100 MHz (data_latch)?

[Altera_Forum]

--- Quote Start ---  I'm also working with ADS5263 just now. What kind of board do you use? I mean is it your custom board or evaluation? I had some problems with LVDS termination. I used 100 Ohms external resistors for LVDS differetial termination and noticed that AC amplitude between positive and negative lines on bit clock line is differente: 270 mV and 600 mV respectively. Furthermore when board's temperature went high, amplitudes went low and PLL unlocked on 40-50 C degrees. The sitaution becomes better after I soldered resitors out of the board and enabled on-chip differential terminator. And one more quastion about synchronization. Do you use PLL dynamic phase shift? If so what clock are you shift 800 MHz, 100 MHz (enable) or 100 MHz (data_latch)?  --- Quote End ---   My board is altera cyclonevGT dev board. I use internal 100R fpga termination (which tool you use to see the bit clock of 400MHz?) you need a good oscilloscope.. I use 1 PLL in lvds mode. The clock_in of pll is the 400 mhz bit clock from adc. PLL out1 -> 800 Mhz phase 0 50% duty (to clock dedicate lvds serdes) PLL out2->100 MHz phase 0 13% duty (to load dedicate lvds serdes). PLL out3->100 MHz phase0 50% duty (to other logic ). At power up i set the adc 2 wire per channel, and send to fpga the synk code (0x0f) for align the serdes..(via the dedicated pin of serdes)

[Altera_Forum]

Hello luca,  

 we are using same ads5263 EVM board for our approach, will you please explain how did you resolve your problem without using frame_clock, we are using it 2 wire 16-bit mode.

[Altera_Forum]

The adc has a bit alignament function. The device send Fixed words for you. The serdes has a bit shift function. You must shift while you read the fixed words.