CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Does Altera publish detailed device pinout drawings like the attached pdf, which was printed from the Pin Planner? Or is the Pin Planner the only place to get this? Seems like these drawings used to be in a document somewhere.
I've seen them on the front page of schematics supplied by Altera and Terasic for dev boards, but never been able to produce one myself. Would be interested in where they come from, if they can be generated by a user.
