help for audio codec using VHDL

[Altera_Forum]

i am a begineer at using altera DE2 board and VHDL. i have to complete my project with in 10 days time but dont have any idea of where to start and how.. help ......... 

i need to build a duplex audio system that works similar to a phone but here CDMA must be considered.  first i would like to have some good advice on where to start and how .... on audio CODEC  any help would be more than appreciated

[Altera_Forum]

--- Quote Start ---  first thank you for your replies.  i tried both a ported version and the original verilog i2c controller (as your audio_codec_controller requests ans i2c_controller component).  during lunch break i made a new project and i was not able to reproduce "varying static". but static is still present when sw1&9 are up (adc dac loopback), as moou pointed out, with or without input signal on line in - i've tried different i/o audio sources and the problem persists.  initialization works fine as expected (5 on hex0) and sine/square wave generation works well too.  maybe i'm missing some macroscopic point. anyways thank you for your help. best regards cb  --- Quote End ---    Hey cb,  Two things I would recommend are:  1. Check the initialization commands to the registers for the audio codec. Make sure they are correct. 2. A very useful check would be to use SignalTap (or an external logic analyzer) and make sure the timing on the i2c bus lines and the left-channel/right-channel lines are correct. In my original design, I had a the dreaded "off by one clock cycle" bug.  Again, I can only finish debugging the audio codec in a couple of weeks. In the meantime, do 1. and 2. above and repost if you find the bug.  Bart

[Altera_Forum]

Hi, 

 I found this topic and it helped me alot. I spent a lot of hours in laboratory and have some problems with i2c.  What does it mean to "resythesize" verilog file? Does it mean to write it from scratch to vhdl file bo looking on verilog code? Or maybe there is some function in Quartus which does such thing (I can't find it in Quartus 9, I'm getting 10.1 now).  Maybe you could please post your project or implementation of i2c_controller for DE2? By looking on it I will try to figure out why my project doesn't work.  Best regards,  Mon

[Altera_Forum]

--- Quote Start ---  Hi,  I found this topic and it helped me alot. I spent a lot of hours in laboratory and have some problems with i2c.  What does it mean to "resythesize" verilog file? Does it mean to write it from scratch to vhdl file bo looking on verilog code? Or maybe there is some function in Quartus which does such thing (I can't find it in Quartus 9, I'm getting 10.1 now).  --- Quote End ---    No synthesis does not mean mapping verilog to VHDL. Synthesis means to obtain a "hardware design" from your verilog or VHDL specification. This hardware design can be of many forms: register-transfer level (RTL), state-machine or even at the "technology-map" level.  Ultimately, synthesis results in a file that can be placed and routed on your FPGA. For more information, read:  www.altera.com/literature/manual/intro_to_quartus2.pdf (http://www.altera.com/literature/manual/intro_to_quartus2.pdf)    --- Quote Start ---  Maybe you could please post your project or implementation of i2c_controller for DE2? By looking on it I will try to figure out why my project doesn't work.  --- Quote End ---  The design for the DE1 and DE2 should be the same because both boards use the same audio codec. However, correctly map the pin assignments from my project for the DE1 to the DE2.   Good luck.  Bart

[Altera_Forum]

Thank you for your reply.  

 I decided to rewrite i2c_controller.v to i2c_controller.vhd by my own hands. It works fine, just had to change name of some ports etc. :)  Thank you for posting your code in tihis topic, it was very helpfull.  Best Regards,  Mon

[Altera_Forum]

I'll make you know. 

Best regards cb

[Altera_Forum]

Thank you for your reply.  

 I decided to rewrite i2c_controller.v to i2c_controller.vhd by my own hands. It works fine, just had to change name of some ports etc. :) monmanmon, can u pls post/send me the i2c_controller that u have done? I really need it.   thank you..:)

[Altera_Forum]

hello everyone. there is something that i am confuse about. how can i call the data from wm8731 so that i can process it into my own processing block before i can send it back to the chip ?

[Altera_Forum]

--- Quote Start ---  The code should be published at the Altera Wiki. It's much more instructive than the respective Terasic demonstration projects.  --- Quote End ---    Finally, I have the time this year to publish the stuff we develop. Anyway, altera wiki (http://www.alterawiki.com/wiki/de1_board)has been updated. direct link (http://myweb.msoe.edu/muthuswamy/digitalsystemsdesign/digitalsystemsdesign.html) to our digital systems website.  I will be making changes to the Altera Wiki and Digital Systems Website once/week (approximately Friday, around 5:00 pm CST) with new reference designs and bug fixes.  Thanks.  Bart

[Altera_Forum]

First thank you for sharing this. It is clear and easy to read. But even with the most updated version I still have static when trying to playback the input signal. Do you not have this issue when running it? And if not why would my setup differ? I am using a DE1 with the 2C20F484C7 chip. Thank you

[Altera_Forum]

--- Quote Start ---  First thank you for sharing this. It is clear and easy to read. But even with the most updated version I still have static when trying to playback the input signal. Do you not have this issue when running it? And if not why would my setup differ? I am using a DE1 with the 2C20F484C7 chip. Thank you  --- Quote End ---    The audio codec interface has been redesigned from scratch (modelSim simulation of the i2c controller, signalTap verification of the adc/dac data registers etc.):  http://myweb.msoe.edu/muthuswamy/digitalsystemsdesign/ee3921/audio/vhdl/de1audioadcdac.zip  Note that you should modify the design above to suit your requirements. Good luck.  Bart

[Altera_Forum]

hi  

I'm trying to get the sound from adc and send the data to the dual port ram and i will control the system with nios but the most important part :when we get the data from WM8731; ı want to check the data like the leftdata and the right data . one port of ram will take the right data ,the other port of ram will take the leftdata .can you help me ? after that i will take fft so complicated . ı run your adcdac controler code   and at first and second trying it is compiled. but now it is not . ı hear the voice from only left side .  ın wm8731 datasheet some parameters (for ex. chipselect volume and etc but where did you define to use the left or right side ? how can use 2 part ?please help :S

[Altera_Forum]

--- Quote Start ---  hi   I'm trying to get the sound from adc and send the data to the dual port ram and i will control the system with nios but the most important part :when we get the data from WM8731; ı want to check the data like the leftdata and the right data . one port of ram will take the right data ,the other port of ram will take the leftdata .  --- Quote End ---    Usually, you use one port of RAM for input and the other for output. I am thinking you are making both ports read/write?  I would have one RAM for left channel data and another RAM for right channel data.    --- Quote Start ---   ı run your adcdac controler code  and at first and second trying it is compiled. but now it is not . ı hear the voice from only left side .  ın wm8731 datasheet some parameters (for ex. chipselect volume and etc but where did you define to use the left or right side ? how can use 2 part ?please help :S  --- Quote End ---  You can't "run" my "code". You mean that you are synthesizing my hardware description.  Anyway, I have reposted a student project in the link above. It also includes a detailed report on how the design works (check Report folder). In addition, the student project also includes simulating a set of nonlinear differential equations using Euler's method (note that this was originally Cornell University's Differential Analyzer, as cited in the project).   This should hopefully help you in understanding how to send data to and from the audio codec to a module (in this case neuronModel.vhd). You should configure the mega IP wizard FFT module and use it instead of the neuronModel.  Good luck.  Bart

[Altera_Forum]

Hey.. I am new to VHDL..I have been trying to implement the code provided.if you have the file for pin assignments please attach it here. 

 regards, Amit

[Altera_Forum]

--- Quote Start ---  Hey.. I am new to VHDL..I have been trying to implement the code provided.if you have the file for pin assignments please attach it here.  regards, Amit  --- Quote End ---    The pin assignments have already been imported. If you want the DE1 pin assignments, you can get them from the DE1 CD-ROM on Terasic's website:  http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=53&no=83&partno=4

[Altera_Forum]

hi mbharat........  

 the DE1 use cyclone 2 FPGA??????    i had two board .... DE2 and cyclone 3 dev board and i wanna port your code to my boars........   the DE2 is better to do it i guess.......   another question..... about the pin clock_27[1..0] .... you conect this pin to a external clock???   and gpio_0[35..0] where i need conect this?????     i2c pins are used for what???? to configure ?????     thank u to post     cheers   Franz Wagner

[Altera_Forum]

--- Quote Start ---  hi mbharat........    the DE1 use cyclone 2 FPGA??????    i had two board .... DE2 and cyclone 3 dev board and i wanna port your code to my boars........   the DE2 is better to do it i guess.......  --- Quote End ---    You can port the hardware to an FPGA board that contains the Wolfson WM8731 audio codec.     --- Quote Start ---  another question..... about the pin clock_27[1..0] .... you conect this pin to a external clock???   and gpio_0[35..0] where i need conect this?????     i2c pins are used for what???? to configure ?????   --- Quote End ---  If you download DE1AudioAdcDac.zip from the link in this thread and unzip it, you should find a project report under the Report folder. Read and understand that report, it answers all your questions.  Bart

[Altera_Forum]

hi ....... thanks to reply 

 yeah ... the DE2 had this audio codec........   i read the documentation..... and its works!!!!   did you use this project to simulate neural network?????????     thank you man......   Franz Wagner

[Altera_Forum]

--- Quote Start ---  hi ....... thanks to reply   yeah ... the DE2 had this audio codec........   i read the documentation..... and its works!!!!   did you use this project to simulate neural network?????????  --- Quote End ---    Glad to hear it works, no we did not use it to simulate a neural network. That was one of the potential applications but we have no time since our school is on a quarter system.   Actually the problem is not simulating a neural network but rather how to make the network learn something useful. The neuron model that we use can also be used to simulate tens of thousands of cortical spiking neurons on a PC in real-time (with 1 ms resolution):  http://www.izhikevich.org/publications/spikes.pdf  Bart

[Altera_Forum]

hi .... 

 good job .........very good  DE2 and DE1 are too much similar............i only change few pins  i work with video/ip and uclinux under nios2 but i was very interested in researching this subject .....thanks  cheers  Franz Wagner

[Altera_Forum]

hii 

i hav just started using vhdl.For now i hav to store the sampled audio signal and then perform fft on it.for the first part,i went through the codes posted above.i dint get how do i compile all source files in one project or do i hav to try and convert into a single file.plz help. thanks.

[Altera_Forum]

Thats not very descriptive of your problem. Are you basically saying to dont know how to use quartus? 

 Go to project -> add files to project to add multiple files.