how do i speed up place&route timing in cyclone V

[Altera_Forum]

Hi, 

  I need help to find a way to speed up fitter time because it takes me over 4 hrs to done the fitter. my sdc file is not complicated and only 76% of usage for device resource. I don't know why what cause cyclone V take so long to do the fitter.  Thanks, Jeff

[Altera_Forum]

Perhaps you need a faster PC.

[Altera_Forum]

--- Quote Start ---  Perhaps you need a faster PC.  --- Quote End ---    Hi,   One more question, I have some logic which using negative edge clock to quality the signal. Would this negedge clk cause longer time to do fitter?  Thanks, Jeff

[Altera_Forum]

--- Quote Start ---  Hi,   I need help to find a way to speed up fitter time because it takes me over 4 hrs to done the fitter. my sdc file is not complicated and only 76% of usage for device resource. I don't know why what cause cyclone V take so long to do the fitter.  Thanks, Jeff  --- Quote End ---    >70% device usage can be significant usage, depending on the size of your device. I run around 1h 10m on a Cyclone V SX with an HPS, using almost every DSP and memory block. This can balloon significantly if I leave floating inputs/outputs in the design. The best thing is to have a completely constrained design, both in connections and in timing. The more open variables you give the compiler, the more difficult it is for it.  I'd take a look at your clock-crossing timing constraints, any parts that are optimized out, and check every warning that you get, line-by-line. As long as you set the correct constraints for the negative edge clock, you shouldn't have an issue, but it does matter depending on how you generate the clock!

[Altera_Forum]

4 hours doesn't sound too unreasonable. I have a 4hr build on a stratix 4 on a 16 core xeon with 48gb ram. It's tight timing and a v full device that causes the long build.  

 Have you got everything false pathed that needs to be? Multi cycle paths? How about logic locking the tight areas?