on chip memory does'nt work with 150 MHz on Cyclone V E development kit

[töz00]

hello dear Intel,

I am using Cyclone V E development kit. I set up a simple nios system(clock-pll-nios II processor- onchip memory-jtag uart) . This system runs with 50 MHz clock frequency. When i raise clock frequency to 150 MHz , system gives me an error (processor pausing and reset failed ). i can work with sdram at 150 MHz but . couldn't run with on chip memory. Does anybody know why this happens?

[sstrell]

It would be necessary to set up timing constraints and perform a timing analysis to verify where the failure is occurring.

Also, which version of the Nios II are you using: e (no license needed) or f?

#iwork4intel

[EricMunYew_C_Intel]

Hi, Steven

You may need to run timing analysis in Quartus, make sure there is no timing errors.

For example,

create_clock -period "150 MHz" -name {clk} {clk}

derive_pll_clocks

The timing report will tell you the max. frequency you can run, or you have to do place and route to improve timing.

Thanks.

Eric

[EricMunYew_C_Intel]

Hi, Steven

Can we close this case ?

Thanks.

Eric

[töz00]

sorry for answer late. Yes I solved my problem. You can close this case.

Thank you for your support!

[EricMunYew_C_Intel]

Alright, thanks Steven.