Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

signal tap Issues

Altera_Forum
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I have a stratix IIGX board that is in a tower computer attached Via PCIe. I am programming from my laptop sitting right next to it via Jtag. I compile the code and sucessfully loaded the .sof file into the board. (I cannot load a .jic file as the board is old we cannot get a replacement and one needs quartus 6.0 to get the ram up and running) 

I then click on the signal tap file and try to run it but I keep getting a jtag error 

 

"CAUSE:You tried to run the SignalTap II Logic Analyzer. However, the SignalTap II Logic Analyzer cannot run because of a JTAG communication error.ACTION:Make sure the circuit board is powered on and programming hardware is connected properly, and re-attempt to run the SignalTap II Logic Analyzer. 

 

 

Here is a picture of the screen 

 

see attachment.  

 

Does anyone know what I am doing wrong? this is driving me nuts. 

The board has to be restarted as it sits in the computer once the code has been loaded. This is done. I cannot seem to link to it at all even though I can program it.
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Altera_Forum
名誉分销商 II
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try flipping the device from the MAX to the Stratix

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Altera_Forum
名誉分销商 II
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Thanks. I did that. Do I need to recompile it? 

 

Bill
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Altera_Forum
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no, you're just telling STP which device to talk to on the JTAG chain

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