what is the function of reset input signal for altera FPGA?

[zlan01]

after powering on , nobody will operate the reset key to reset the Altera fpga , how can the reset key to act the reseting function? or after powering on ,after the altera fpga is configured, another reset signal will be defaulted to add to the input reset signal from the outside key ?

[YuanLi_S_Intel]

Hi Zhang Lan,

May i know which reset are you referring to? Are you refering to the reset pin of an IP? or the nCONFIG pin to make FPGA into reset?

Thank You

[zlan01]

I refer to ​ the reset pin of an IP , and the verilog or VHDL module of the project

[YuanLi_S_Intel]

So, you are looking for the method to reset the IP in FPGA? If it so, there are few ways to do that, you can write your own VHDL, have a reset pin connected to input or you can use "platform designer" and it will automatically instantiate a master reset block for you. Then, apply an input pin to that reset block.