Can PEBS sample every event?

[barbito]

TL;DR:
Is it possible to sample every event with PEBS? With my experiments I wasn't able to get  more than  1/2 samples (i.e. sample 1 captured, sample 2 missed, sample 3 captured, etc.)

Long version:
I am trying to sample with PEBS every mispredicted branch. I wrote a simple Linux kernel module to setup all the PEBS-related registers and I managed to get it working.

From the initial results it seemed PEBS was missing some events. So I added 100 nops between every instruction to avoid "ghosting" and switched to an architectural event (branch taken).

To my surprise, PEBS successfully capture only 1 sample out of 2 with reset value set to -1. These are my results changing the reset value in the Debug Store "PEBS GP Counter 0 Reset" field:

• Reset value -1:   1/2 events
• Reset value -2:   1/3 events
• Reset value -3:   1/4 events
• ...

Obviously when I use 0 as reset value I don't get any samples since 2^48 events must occur.

Is this an architectural limitation, or am I missing something?

Thanks!

[barbito]

I found a temporary solution: use 2 GP counters and interleave them:

ds->pebs_reset[0] = -1;
ds->pebs_reset[1] = -1;

//When starting PEBS
wrmsrl(MSR_IA32_PERFCTR0, -1);
wrmsrl(MSR_IA32_PERFCTR1, -2);

With this setup the majority of time I am able to capture all the samples, however sometimes the counters synchronize and the issue is back.
Any hints for a more elegant solution?

[barbito]

Ah so apparently is a feature, not a bug

From SDM 19.3.1.1 Enhancements of Performance Monitoring in the Processor Core inside 19.3.1 Performance Monitoring for Processors Based on Nehalem Microarchitecture

Performance monitoring interrupts are triggered by a counter transitioning from maximum count to zero (assuming
IA32_PerfEvtSelX.INT is set). This same transition will cause PEBS hardware to arm, but not trigger. PEBS hard-
ware triggers upon detection of the first PEBS event after the PEBS hardware has been armed (a 0 to 1 transition
of the counter). At this point, a PEBS assist will be undertaken by the processor.