100G core missing SOP/EOP handling on TX

[DanD]

How does the Stratix 10 low-latency 100G core handle missing SOP or EOP on its TX interface? (l8_tx_*)?

[Deshi_Intel · Accepted solution]

Hi,

I would expect the Tx MAC IP to wait for the completion of either missing SOP or EOP then assert l8_txstatus_error[6:0].

However, this issue shouldn't happen in the first place and should be taken care by the HOST application.

• If worst case there is issue with transmitted packet then I expect the HOST application to assert "l8_tx_error" to alert TX MAC IP

Feel free to play around and test it out in simulation design

Thanks.

Regards,

dlim