FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6492 Discussions

100G core missing SOP/EOP handling on TX

DanD
Beginner
506 Views

How does the Stratix 10 low-latency 100G core handle missing SOP or EOP on its TX interface? (l8_tx_*)?

0 Kudos
1 Solution
Deshi_Intel
Moderator
492 Views

Hi,


I would expect the Tx MAC IP to wait for the completion of either missing SOP or EOP then assert l8_txstatus_error[6:0].


However, this issue shouldn't happen in the first place and should be taken care by the HOST application.

  • If worst case there is issue with transmitted packet then I expect the HOST application to assert "l8_tx_error" to alert TX MAC IP


Feel free to play around and test it out in simulation design


Thanks.


Regards,

dlim


View solution in original post

0 Kudos
1 Reply
Deshi_Intel
Moderator
493 Views

Hi,


I would expect the Tx MAC IP to wait for the completion of either missing SOP or EOP then assert l8_txstatus_error[6:0].


However, this issue shouldn't happen in the first place and should be taken care by the HOST application.

  • If worst case there is issue with transmitted packet then I expect the HOST application to assert "l8_tx_error" to alert TX MAC IP


Feel free to play around and test it out in simulation design


Thanks.


Regards,

dlim


0 Kudos
Reply