FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6359 Discussions

Avalon MM slave component: readdata signal is always zero

MateusSoares
Beginner
471 Views

I have this simple Avalon MM slave component where I set avs_s0_readdata to a constant value:

MateusSoares_1-1670611379196.png

But avs_s0_readdata always stays with value zero. I've tried to achieve this in three different ways, showed in the code commented. Look at this signal tap logic analizer:

MateusSoares_2-1670611724744.png

readdata is always 0h, even when read signal is enabled. Shouldn't readdata be always the constant value I set in the component's code? 


0 Kudos
4 Replies
RichardTanSY_Intel
434 Views

Do you see the same behavior when you try to simulate the design?

Btw, may I know which Quartus edition and version are you using?

Which device are you using?


Best Regards,

Richard Tan


0 Kudos
sstrell
Honored Contributor III
423 Views

Your clk is not toggling according to Signal Tap, so a better question may be how the writes are working!

0 Kudos
RichardTanSY_Intel
382 Views

Any update on this?


Regards,

Richard Tan


0 Kudos
RichardTanSY_Intel
361 Views

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thank you.


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


0 Kudos
Reply