FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Avalon to external bus bridge

KSwam3
Beginner
‎02-28-2019 05:30 PM
1,176 Views

Hi,

 

I need to use this bridge to control my custom IP from an Avalon MM master. The external bridge has signals ACK and IRQ which are not part of my custom IP. Should i still use these signals, or can i safely ignore them?

 

Thanks

SKa

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Kenny_Tan
Moderator
‎03-11-2019 06:33 AM
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Yes, qsys/synthesis will show error if it is not allowed.
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