FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

DDR II SRAM (not SDRAM) interface to Stratix II

FFT - block floating point scaling (AN 404)

What USB Phy would bolt up to a CAST CUSB core?

PAL-to-NTSC Conversion IP

Does Altera support ZBT SRAM for Stratix II devices?

Does Altera have USB 2.0 host core?

ALT2GXB: Disableing 8b10b in basic mode

DSP Builder with open source Simulink alternative

Xray image enhancement using VIP suites

How to hook up external functions into Simulink blocks in DSP Builder

Altmemphy

Wishful feature for DSP Builder

FIR: getting coef_ld to show up in DSP Builder

Alpha Blending Mixer and Gamma Corrector - Changes to control registers

MCV architecture for FIR v6.1

Featured Content

Which FPGA IP can be used FREE in production with the Quartus LITE dev. sw?

Can we generate EMIF DDR4 without mem_alert_n or not connect the emif_alert_n in the instantiation

Agilex 7 M EMIF Mode Register Access