FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
公告
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
6673 讨论

Avalon to external bus bridge

KSwam3
初学者
1,544 次查看

Hi,

 

I need to use this bridge to control my custom IP from an Avalon MM master. The external bridge has signals ACK and IRQ which are not part of my custom IP. Should i still use these signals, or can i safely ignore them?

 

Thanks

SKa

0 项奖励
1 回复
KennyTan_Altera
主持人
945 次查看
Yes, qsys/synthesis will show error if it is not allowed.
0 项奖励
回复