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Hallo together,
actually i'm trying to implement a system with the hard PCIe core of the Cyclone 5 Altera development board (GX). What do I use - Quartus 13 on a windows 64 bit computer - PCIe development board from Altera - Embedded pc from Kontron with Linux - Avalon-MM Cyclone V Hard IP for PCI Express What is working: - Linux detects the different bars and loads the correct driver. - Access through different PCIe bars to internal and external ram (ddr3). What is NOT working: - Can't enable the Interrupt because I can't read and write the CRA register area How do I test: - The CRA register are mapped through a slave in the Avalon address space (0x0 - 0x3FFF) - Avalon Master of BAR 2 is connected to this slave an to an additional SRAM slave - I can read and write to the slave - verified also with the signal tap - I can realize a read and write to the CRA slave - signal tap to the port of the slave - signal names like dut_cra_translator/av_address etc. - When the BAR2 master write and read I can see the correct values (adr, data, ... ) - I can see the the wait_request is deactivated after on clock or so. - But I always read zero (and I do not write zero :)). Does anyone know what's wrong? best regards ArndLink Copied
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Hi Arnd,
we are having the same problem. Would you please tell us if you found the reason and how to solve the problem. Thanks in advance.- Mark as New
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Hi,
I am having the same problem. Has anyone found a solution to this, or a reason why the CRA registers appear to be all set to zero? I am also using the Altera CycloneV GX dev board with the 5CGXFC7D6F31C6NES and Quartus 13.1. I set values to the ID registers (Vendor ID, Device Id, etc..) in the QSys IP set-up GUI for the "Avalon-MM Cyclone V Hard IP for PCI Express" (altera_pcie_cv_hip_avmm). I expected to see these same values when accessing the CRA register from the NIOS2 processor. All I see is zeros. I am setting up the Hard IP as a Root Port. I'm still learning about PCIe, so my assumption that the CRA port should show something useful may be wrong. I would be greatful is somebody could at least confirm what I should be seeing through the CRA port. Thanks.- Mark as New
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--- Quote Start --- Hi, I am having the same problem. Has anyone found a solution to this, or a reason why the CRA registers appear to be all set to zero? I am also using the Altera CycloneV GX dev board with the 5CGXFC7D6F31C6NES and Quartus 13.1. I set values to the ID registers (Vendor ID, Device Id, etc..) in the QSys IP set-up GUI for the "Avalon-MM Cyclone V Hard IP for PCI Express" (altera_pcie_cv_hip_avmm). I expected to see these same values when accessing the CRA register from the NIOS2 processor. All I see is zeros. I am setting up the Hard IP as a Root Port. I'm still learning about PCIe, so my assumption that the CRA port should show something useful may be wrong. I would be greatful is somebody could at least confirm what I should be seeing through the CRA port. Thanks. --- Quote End --- Hi, Have you tried Quartus 13.0? This may work. Or you can connect a BAR directly to CRA port and control from CPU/PC. Good luck.
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Hello, I'm having the same problem. All I read from CRA (register data) is zero ... Thank you in advance for any hint.
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If you are using VHDL, if so you might be running into this known issue:
http://www.altera.com/support/kdb/solutions/rd03062014_662.html- Mark as New
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Thank you memory_monkey :) for your help -> it solved my problem.
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Hi,
Could you show me a example about how to operate with CRA register from the NIOS2 processor?. Thanks
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