Stratix 10 Dual-Port RAM (with 2 clocks) generation problem

[Amir_Nassie]

Hi,

i'm converting my Stratix V design to Stratix 10.

in Stratix V i used the MegaWizard in quartus (13.1 i think) to create an SRAM with:

• 2 read+write ports
• 512 rows of 128bits each (same data bus width on both ports)
• different clock for each of the ports
• byte_enable support on both ports

using QuarusPro "IP Catalog" i tried to get the same SRAM functionality.

i used the "memory user guide" from Intels website

at section 4.1.3. RAM: 2-PORT Intel FPGA IP Parameters

In the optional clocking schemes for the generated SRAM.

There is an option for different clocks for the 2 ports (A & B)

When I try to generate the SRAM in the IP Catalog. I configure the parameters as follows :

Then

And then

When coming to select the clocking scheme, I do not see the suggested option by the DOC.

If selecting "Customize clocks for A and B ports"

I can not use byte_enable on the ports

please advise.

Best Regards,

Amir Nassie

[sstrell]

I think there's a disconnect between the documentation and the parameter editor.  I believe that the "Customize" option is what you need to select, but are you saying that when you do that, the byte_enable options for the two ports that you show in your last screenshot disappear?  I don't have the software open at the moment to check this.

[Amir_Nassie]

Hi,

thanks for the help.

yes, i agree regarding the possibly misleading documentation. (who is authorized to approve that?)

regarding the "Customize clocks for A and B ports",
yes it is impossible to generate byte_enable for the ports.

when selecting such clocking scheme i get the below error :

Error: stx10_fpga_dpmram512x128.ram_2port_0: In 'Clks/Rd, Byte En' tab, 'Emulate TDP dual clock mode' must be enabled if clocking method is 'Customize clocks for A and B ports' for Stratix 10 while using two read/write ports.

So I'm adding the TDP emulation check mark.

Then I select to have byte_enable (for port A for example)

And get the below error

Error: stx10_fpga_dpmram512x128.ram_2port_0: In 'Clks/Rd, Byte En' tab, 'Byte Enable Ports' are unavailable while using 'Emulate TDP dual clock mode' feature.

[JohnT_Intel]

Hi,

I would recommend you to use "Dual Clock: use separate 'input' and 'output' clocks" setting.

[Amir_Nassie]

Thanks,

but how do i get the 2 read+write ports (each in a different clock domain) functionality ?

[JohnT_Intel · Accepted solution]

Hi,

If you look into https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-memory.pdf Table 10, it will shows that Stratix 10 does not support True Dual Port with byte enable features.