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The above answer record mentions that the error is generated when an EMIF IP with HPS is used for simulation. I am using the EMIF IP for DDR4 and the device used during output products generation is a Stratix 10 GX part which does not have HPS.
Can you please point me towards some possible causes of this error?
Simulator: xcelium2019.09_s007
Quartus Prime Pro 19.4
Thanks
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Hi @alinaveā ,
It's me Aida. š I believed this is similar issue with what you've posted in below thread. I have provided my reply in below thread.
https://forums.intel.com/s/question/0D50P00004bZOyx/emif-ip-fetches-error-while-simulating-in-vcs
Since you created this new case and this case just re-routed today to me , I suggest we continue our discussion using this new case. Let me know if you have any concern.
I copy my reply again here for tracking purpose:
Have you try to used this supported tools version for Xcelium for Quartus 19.4?
Also may I know which memory simulation model are you using (for example Micron or etc)?
Thanks
Regards,
Aida
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Hi Aida,
Thanks for your reply. I will check the simulation results with 2018.03 xcelium version. I have been using Micron memory model.
Thanks,
Naved
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Hi Naved,
Thanks for the confirmation regarding memory model. I reached out to our internal engineering team for assistance and they are telling me we do not support vendor models since they have very stringent checks trigger during calibration. I also re-confirmed the statement on our documentation and it does state that we do not support these models. See Below.
Sincerely sorry I do not have better news for you. But, please let me know if there is anything more I can help.
Thanks
Regards,
Aida
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Hi Aida,
I tried the Intel provided model and the earlier version of xcelium but got the same error at exactly the same time..
Thanks,
Naved
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Dear Naved,
Please accept my apology for the delay in response due to recent workload.
Is it possible to have the design (with Intel provided model) to look closer?
Thanks
Regards,
Aida
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